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Table of Contents

EVALUATING THE AD9680/AD9690/AD9234 ANALOG-TO-DIGITAL CONVERTER

Preface

This user guide describes the AD9680/AD9234 evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. Users wanting to evaluate the single channel AD9690 should utilize/evaluate Channel A on the AD9680-500EBZ, or AD9680-1000EBZ. The application software used to interface with the devices is also described. This user guide wiki applies to the following evaluation boards:

Evaluation Board Part Number Description Board Revision
AD9680-1250EBZ Evaluation board for AD9680-1250; Full Bandwidth 9680CE04B
AD9680-1000EBZ Evaluation board for AD9680-1000; Full Bandwidth 9680CE04B
AD9680-820EBZ Evaluation board for AD9680-820; Full Bandwidth 9680CE04B
AD9680-500EBZ Evaluation board for AD9680-500; Full Bandwidth 9680CE04B
AD9234-1000EBZ Evaluation board for AD9234-1000; Full Bandwidth 9680CE04B
AD9234-500EBZ Evaluation board for AD9234-500; Full Bandwidth 9680CE04B
AD9680-LF1000EBZ Evaluation board for AD9680-1000; up to 1GHz Input Bandwidth 9680CE02B
AD9680-LF820EBZ Evaluation board for AD9680-820; up to 1GHz Input Bandwidth 9680CE02B
AD9680-LF500EBZ Evaluation board for AD9680-500; up to 1GHz Input Bandwidth 9680CE02B
AD9234-LF1000EBZ Evaluation board for AD9234-1000; up to 1GHz Input Bandwidth 9680CE02B
AD9234-LF500EBZ Evaluation board for AD9234-500; up to 1GHz Input Bandwidth 9680CE02B


The AD9680 and AD9234 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to highspeed.converters@analog.com.

AD9680/AD9234 Evaluation Board

Figure 1. AD9680/AD9234 Evaluation Board for full 2GHz Input Bandwidth

Figure 2. AD9680/AD9234 Low Frequency Evaluation Board up to 1GHz Input Bandwidth

Figure 3 below compares the bandwidth available on the AD9680/AD9234 normal evaluation boards and the “LF” boards

Figure 3. Comparison of Bandwidth on the Normal and the “LF” boards

Typical Measurement Setup

The AD9680-1000EBZ/AD9234-1000EBZ can be evaluated using the ADS7-V2EBZ FPGA data capture boards. Figures 3 and 4 below show the AD9680-1000EBZ/AD9234-1000EBZ connected to the ADS7-V1EBZ and ADS7-V2EBZ respectively.

Figure 3. Evaluation Board Connection—AD9680-1000EBZ/AD9234-1000EBZ (on Left) and ADS7-V1EBZ (on Right)

Please note : ADS7-V1EBZ has been obsoleted and is NOT recommended for new evaluations.

Figure 4. Evaluation Board Connection—AD9680-LF1000EBZ/AD9234-LF1000EBZ (on Left) and ADS7-V2EBZ (on Right)

Features

  • Full featured evaluation board for the AD9680 and AD9234. Includes
    • AD9680-1000EBZ, AD9680-LF1000EBZ
    • AD9680-820EBZ, AD9680-LF820EBZ
    • AD9680-500EBZ, AD9680-LF500EBZ
    • AD9234-1000EBZ, AD9234-LF1000EBZ
    • AD9234-500EBZ, AD9234-LF500EBZ
  • SPI interface for setup and control
  • Wide band Balun driven input for the AD9680-1000EBZ, AD9680-820EBZ, AD9680-500EBZ, AD9234-1000EBZ and AD9234-500EBZ
  • Double balun input for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ and AD9234-LF500EBZ
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC
  • VisualAnalog® and SPI controller software interfaces
  • On-board Crystal oscillator for AD9680-LF1000EBZ, AD9234-LF1000EBZ, AD9680-500EBZ, AD9234-LF500EBZ

Helpful Documents

Software Needed

Design and Integration Files

Equipment Needed

  • Analog signal source and antialiasing filter
  • Sample clock source
  • 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ)
  • PC running Windows®
  • USB 2.0 port
  • AD9680 or AD9234 Evaluation board
  • ADS7-V2EBZ FPGA-based data capture kit

Getting Started

This section provides quick start procedures for using the evaluation board for AD9680 or AD9234.

Configuring the Board

Before using the software for testing, configure the evaluation board as follows:

  1. Connect the evaluation board to the ADS7-V2EBZ data capture board, as shown in Figure 2.
  2. Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the ADS7-V2EBZ board. Connect the Standard-B USB port of the ADS7-V2EBZ board to the PC with the supplied USB cable.
  3. Turn on the ADS7-V2EBZ.
  4. The ADS7-V2EBZ will appear in the Device Manager as shown in Figure 3.

    Figure 4. Device Manager showing ADS7-V1EBZ

  5. If the Device Manager does not show the ADS7-V2EBZ listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
  6. On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock.
  7. On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:

    LaneLineRate=M*Nprime*(10/8)*f_{out}/Lbps/lane, where

    f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16(Default Nprime = 16)

    REFCLK = LaneLineRate/20

  8. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  9. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)

Visual Analog Setup

  1. Click Start right All Programs right Analog Devices right VisualAnalog right VisualAnalog
  2. On the VisualAnalog “New Canvas” window, click ADCrightDualrightAD9680 or ADCrightDualrightAD9234

    Figure 5. Selecting the AD9680 canvas

  3. At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 6. Programming the FPGA will provide power to the evaluation board.

    Figure 6. Programming the ADS7-V2EBZ

  4. If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 7)

    Figure 7. Expanding Display in VA

  5. Click the Settings button in the ADC Data Capture block as shown in Figure 8

    Figure 8. Changing the ADC Capture Settings

  6. On the General tab make sure the clock frequency is set to the appropriate sample rate (eg. 1000MHz or 500MHz). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADs7-V2 FPGA software supports up to 2M FFT capture (1M per channel)

    Figure 9. Setting the clock frequency and Capture length

  7. On the Device tab. Make sure that Enable Alternate REFCLK option is unchecked.
  8. Click OK

SPIController Setup

  1. Click Start right All Programs right Analog Devices right SPIController right SPIController
  2. Select the appropriate configuration file when prompted.
  3. In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft reset for the DUT.

    Figure 10. Sending a Soft Reset to the AD9680

  4. Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.

    Figure 11. Device Index for ADC Channel A and Channel B

  5. Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:
    1. Chip Configuration Register (0x002): This option allows the channel to be powered on
    2. Buffer Current Setting (0x018): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting.
    3. Analog Input Differential Termination (0x016): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced.
    4. Input Full Scale Range (0x025): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.

Sample Configuration 1: Full Bandwidth Mode

  1. Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register address 0x200 to Full Bandwidth Mode and Chip Decimation Ratio Control Register 0x201 to Full Sample Rate.

    Figure 12. Setting Chip Mode Control and Decimation Ratio Registers

  2. For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).

    Figure 13. JESD204B Serial Transmit Power Down

  3. Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.

    Figure 14. Setting the JESD204B Lane Rate

  4. Set the JESD204B Quick Configuration register (0x570). For 1000MSPS operation with NO DDCs (Full Bandwidth Mode), the values for L.M.F are 4.2.1

    Figure 15. Setting the JESD204B Quick Configuration Register

  5. Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.

    Figure 16. Reading the JESD204B Configuration Registers

  6. On address 0x58F, change the Converter Resolution to 14 for AD9680 (12 for AD9234).
  7. Back to ADCBase3 tab, uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).
  8. After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.

    Figure 17. Reading the PLL Status Register

Obtaining an FFT

  1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 17.

    Figure 17. AD9680-1000 FFT at 170MHz Analog Input

  2. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.)
  3. To save the FFT plot do the following
  4. Click on the Float Form button in the FFT window

    Figure 18. Floating the FFT window

  5. Click on File right Save Form As button and save it to a location of choice

    Figure 19. Saving the FFT

Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4

  1. In the VisualAnalog Setup, follow Steps 1-5 and after that, click the ADC Data Capture Settings, remove Ch.A and Ch.B output data, and add Ch. DDC0 and Ch. DDC1 output data.

    Figure 20. VisualAnalog ADC Data Capture Settings for DDC

  2. In the SPIController Setup, follow Steps 1-4.
  3. Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register (0x200) to Two Digital Down Converters and Chip Decimation Ratio Control Register (0x201) to Decimate by 4.

    Figure 22. Setting Chip Mode Control and Decimation Ratio Registers

  4. For DDC settings, proceed to ADCBase1 tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of 0x310 and 0x330, respectively, to Real Mixer, Variable IF Mode, Complex (I/Q) Decimate by 4. Channel Input Selection for address 0x311 is set to Channel A for I and Q while address 0x331 is set to Channel B for I and Q.

    Figure 23. DDC Control Registers

  5. For frequency tuning word (FTW), addresses 0x314-315 are set as required by application for DDC0, and addresses 0x334-335 are set as required by application for DDC1. Figure xx below shows the calculation for NCO Frequency Tuning Word.

    Figure 24. Frequency Tuning Word Formula

  6. After setting all DDC registers, go to Generic Write/Read in Global tab and write 0x10 to address 0x300 (DDC soft reset), and write back to 0x00 (DDC normal operation). Same process can be done by checking and unchecking the DDC Soft Reset box.

    Figure 25. DDC Synchronization Control Register

  7. For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).

    Figure 26. JESD204B Serial Transmit Power Down

  8. Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.

    Figure 27. Setting the JESD204B Lane Rate

  9. Set the JESD204B Quick Configuration register (0x570). For 1000MSPS operation with 2 DDCs (Two Digital Down Converters), the values for L.M.F are 2.4.4.

    Figure 28. Setting the JESD204B Quick Configuration Register

  10. Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.

    Figure 29. Reading the JESD204B Configuration Registers

  11. On address 0x58F, change the Converter Resolution to 14 for AD9680 (12 for AD9234).
  12. Back to ADCBase3 tab, uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).
  13. After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.

    Figure 30. Reading the PLL Status Register

Obtaining an FFT

  1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 32.

    Figure 32. AD9680-1000 FFT at 150.3MHz Analog Input, NCO_FTW = 155MHz

  2. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.)

Validating Deterministic Latency Using Subclass 1 Operation

The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency differences between subclass 0 and subclass 1 operation. The “Validating Subclass 1 Operation of the AD9680” document will guide the user through the necessary steps to perform this validation. SPI Controller scripts for several full bandwidth modes are included for convenience. ad9680_ads7v2_dl_demo.zip spicontroller_scripts_for_dl_demo.zip

Troubleshooting Tips

FFT plot appears abnormal

  • If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.
  • In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel.
  • Issue a Data Path Soft Reset through SPIController Global tab as shown in Figure 33

    Figure 33. Issuing a data path soft reset through SPIController

The FFT plot appears normal, but performance is poor.

  • Make sure you are using the appropriate band-pass filter on the analog input.
  • Make sure the signal generators for the clock and the analog input are clean (low phase noise).
  • If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
  • Make sure the SPI config file matches the product being evaluated.

The FFT window remains blank after the Run button is clicked

  • Make sure the evaluation board is securely connected to the ADS7-V2.
  • Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the ADS7-V2. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V2 setup process.
  • Make sure the correct FPGA bin file was used to program the FPGA.
  • Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.

    Figure 34. Setting the correct clock frequeency in VisualAnalog

  • Ensure that the REFCLOCK is ON and set to the appropriate frequency.
  • Restart SPIController.

VisualAnalog indicates that the “FIFO capture timed out” or “FIFO not ready for read back”

  • Make sure all power and USB connections are secure.
  • Make sure that the REFCLOCK is ON and set to the appropriate frequency.

VisualAnalog displays a blank FFT when the RUN button is clicked

  • Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 35.

    Figure 35. Clock Detection Status Register

  • Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController.
resources/eval/ad9680-1000ebz.1663918992.txt.gz · Last modified: 23 Sep 2022 09:43 by John Xavier Toledo

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