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resources:eval:ad9680-1000ebz [17 Nov 2022 03:13] – [Equipment Needed] John Xavier Toledoresources:eval:ad9680-1000ebz [23 Oct 2023 08:25] – [Troubleshooting Tips] Janadrian Alipio
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 ====== EVALUATING THE AD9680/AD9690/AD9234 ANALOG-TO-DIGITAL CONVERTER ====== ====== EVALUATING THE AD9680/AD9690/AD9234 ANALOG-TO-DIGITAL CONVERTER ======
 +
 ===== Preface ===== ===== Preface =====
-This user guide describes the [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. Users wanting to evaluate the single channel [[adi>AD9690|AD9690]] should utilize/evaluate Channel A on the AD9680-500EBZ, or AD9680-1000EBZ. The application software used to interface with the devices is also described. This user guide wiki applies to the following evaluation boards: +This user guide describes the [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. Users wanting to evaluate the single channel [[adi>AD9690|AD9690]] should utilize/evaluate Channel A on the AD9680-1250EBZ, or AD9680-1000EBZ. The application software used to interface with the devices is also described. This user guide wiki applies to the following evaluation boards: 
-^ Evaluation Board Part Number      ^ Description       ^Board Revision       +^ Evaluation Board Part Number      ^ Description       ^ Board Revision      
-| <fc #9400d3>AD9680-1250EBZ</fc>    | <fc #9400d3>Evaluation board for AD9680-1250; Full Bandwidth</fc>     | <fc #9400d3>9680CE04B</fc>     +| <fc #9400d3>AD9680-1250EBZ</fc>   | <fc #9400d3>Evaluation board for AD9680-1250; Full Bandwidth</fc>     | <fc #9400d3>9680CE04B</fc>
-| <fc #9400d3>AD9680-1000EBZ</fc>    | <fc #9400d3>Evaluation board for AD9680-1000; Full Bandwidth</fc>     | <fc #9400d3>9680CE04B</fc>     +| <fc #9400d3>AD9680-1000EBZ</fc>   | <fc #9400d3>Evaluation board for AD9680-1000; Full Bandwidth</fc>     | <fc #9400d3>9680CE04B</fc>    
-| <fc #9400d3>AD9680-820EBZ</fc>     | <fc #9400d3>Evaluation board for AD9680-820; Full Bandwidth</fc>      | <fc #9400d3>9680CE04B</fc>     +| <fc #9400d3>AD9680-820EBZ</fc>    | <fc #9400d3>Evaluation board for AD9680-820; Full Bandwidth</fc>       | <fc #9400d3>9680CE04B</fc>    
-| <fc #9400d3>AD9680-500EBZ</fc>     | <fc #9400d3>Evaluation board for AD9680-500; Full Bandwidth</fc>      | <fc #9400d3>9680CE04B</fc>     +| <fc #9400d3>AD9680-500EBZ</fc>    | <fc #9400d3>Evaluation board for AD9680-500; Full Bandwidth</fc>       | <fc #9400d3>9680CE04B</fc>    
-| <fc #008000>AD9234-1000EBZ</fc>    | <fc #008000>Evaluation board for AD9234-1000; Full Bandwidth</fc>    | <fc #008000>9680CE04B</fc>     +| <fc #008000>AD9234-1000EBZ</fc>   | <fc #008000>Evaluation board for AD9234-1000; Full Bandwidth</fc>     | <fc #008000>9680CE04B</fc>    
-| <fc #008000>AD9234-500EBZ</fc>     | <fc #008000>Evaluation board for AD9234-500; Full Bandwidth</fc>      | <fc #008000>9680CE04B</fc>     +| <fc #008000>AD9234-500EBZ</fc>    | <fc #008000>Evaluation board for AD9234-500; Full Bandwidth</fc>       | <fc #008000>9680CE04B</fc>    
-| <fc #4682b4>AD9680-LF1000EBZ</fc>    | <fc #4682b4>Evaluation board for AD9680-1000; up to 1GHz Input Bandwidth</fc>     | <fc #4682b4>9680CE02B</fc>     +| <fc #4682b4>AD9680-LF1000EBZ</fc> | <fc #4682b4>Evaluation board for AD9680-1000; up to 1GHz Input Bandwidth</fc> | <fc #4682b4>9680CE02B</fc>    
-| <fc #4682b4>AD9680-LF820EBZ</fc>     | <fc #4682b4>Evaluation board for AD9680-820; up to 1GHz Input Bandwidth</fc>      | <fc #4682b4>9680CE02B</fc>     +| <fc #4682b4>AD9680-LF820EBZ</fc>  | <fc #4682b4>Evaluation board for AD9680-820; up to 1GHz Input Bandwidth</fc>  | <fc #4682b4>9680CE02B</fc>    
-| <fc #4682b4>AD9680-LF500EBZ</fc>     | <fc #4682b4>Evaluation board for AD9680-500; up to 1GHz Input Bandwidth</fc>      | <fc #4682b4>9680CE02B</fc>     +| <fc #4682b4>AD9680-LF500EBZ</fc>  | <fc #4682b4>Evaluation board for AD9680-500; up to 1GHz Input Bandwidth</fc>  | <fc #4682b4>9680CE02B</fc>    
-| AD9234-LF1000EBZ    | Evaluation board for AD9234-1000; up to 1GHz Input Bandwidth     | 9680CE02B     +| AD9234-LF1000EBZ     | Evaluation board for AD9234-1000; up to 1GHz Input Bandwidth     | 9680CE02B  
-| AD9234-LF500EBZ     | Evaluation board for AD9234-500; up to 1GHz Input Bandwidth      | 9680CE02B     |+| AD9234-LF500EBZ     | Evaluation board for AD9234-500; up to 1GHz Input Bandwidth       | 9680CE02B   |
 \\ \\
 The [[adi>ad9680|AD9680]] and [[adi>ad9234|AD9234]] data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. The [[adi>ad9680|AD9680]] and [[adi>ad9234|AD9234]] data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com.
  
 ===== AD9680/AD9234 Evaluation Board ===== ===== AD9680/AD9234 Evaluation Board =====
-{{ :resources:eval:ad9680evb2.jpg?direct600 |}}<WRAP centeralign> +{{ :resources:eval:ad9680evb2.jpg?direct600 |}} 
-//Figure 1. [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] Evaluation Board for full 2GHz Input Bandwidth//</WRAP> +<WRAP centeralign>//Figure 1. [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] Evaluation Board for full 2GHz Input Bandwidth//</WRAP> 
-{{ :resources:eval:ad9680_lfboard.jpg?direct600 |}}<WRAP centeralign> +{{ :resources:eval:ad9680_lfboard.jpg?direct600 |}} 
-//Figure 2. [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] Low Frequency Evaluation Board up to 1GHz Input Bandwidth//</WRAP> +<WRAP centeralign>//Figure 2. [[adi>AD9680|AD9680]]/[[adi>AD9234|AD9234]] Low Frequency Evaluation Board up to 1GHz Input Bandwidth//</WRAP> 
-Figure 3 below compares the bandwidth available on the AD9680/AD9234 normal evaluation boards and the **"LF"** boards{{ :resources:eval:gain_flatness_compare_ce04b_ce02b_5178_image001.png?direct |}}<WRAP centeralign> +Figure 3 below compares the bandwidth available on the AD9680/AD9234 normal evaluation boards and the **"LF"** boards
-//Figure 3. Comparison of Bandwidth on the Normal and the "LF" boards//</WRAP>+{{ :resources:eval:gain_flatness_compare_ce04b_ce02b_5178_image001.png?direct |}} 
 +<WRAP centeralign>//Figure 3. Comparison of Bandwidth on the Normal and the "LF" boards//</WRAP>
  
 ===== Typical Measurement Setup ===== ===== Typical Measurement Setup =====
-The [[adi>AD9680|AD9680-1000EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] can be evaluated using the [[adi>eval-ads7-v2|ADS7-V2EBZ]] FPGA data capture boards. Figures and below show the [[adi>AD9680|AD9680-1000EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] connected to the [[adi>eval-ads7-v1|ADS7-V1EBZ]] and [[adi>eval-ads7-v2|ADS7-V2EBZ]] respectively.  +The [[adi>AD9680|AD9680-1250EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] can be evaluated using the [[adi>eval-ads7-v2|ADS7-V2EBZ]] FPGA data capture boards. Figures and below show the [[adi>AD9680|AD9680-1250EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] connected to the [[adi>eval-ads7-v1|ADS7-V1EBZ]] and [[adi>eval-ads7-v2|ADS7-V2EBZ]] respectively. 
-{{ :resources:eval:ad9680_setup.jpg?direct&600 |}}<WRAP centeralign> +{{ :resources:eval:ad9680_setup.jpg?direct&600 |}} 
-//Figure 3. Evaluation Board Connection—[[adi>AD9680|AD9680-1000EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] (on Left) and [[adi>eval-ads7-v1|ADS7-V1EBZ]] (on Right)//</WRAP> +<WRAP centeralign>//Figure 4. Evaluation Board Connection—[[adi>AD9680|AD9680-1250EBZ]]/[[adi>AD9234|AD9234-1000EBZ]] (on Left) and [[adi>eval-ads7-v1|ADS7-V1EBZ]] (on Right)//</WRAP> 
-<WRAP>**Please note : ADS7-V1EBZ has been obsoleted and is NOT recommended for new evaluations.** +<note important>**Note: ADS7-V1EBZ has been obsoleted and is NOT recommended for new evaluations.**</note
-</WRAP+{{ :resources:eval:ad9680_setup-new_copy.jpg?direct&600 |}} 
-{{ :resources:eval:ad9680_setup-new_copy.jpg?direct&600 |}}<WRAP centeralign> +<WRAP centeralign>//Figure 5. Evaluation Board Connection—[[adi>AD9680|AD9680-LF1000EBZ]]/[[adi>AD9234|AD9234-LF1000EBZ]] (on Left) and [[adi>eval-ads7-v2|ADS7-V2EBZ]] (on Right)//</WRAP> 
-//Figure 4. Evaluation Board Connection—[[adi>AD9680|AD9680-LF1000EBZ]]/[[adi>AD9234|AD9234-LF1000EBZ]] (on Left) and [[adi>eval-ads7-v2|ADS7-V2EBZ]] (on Right)// +
-</WRAP>+
 ===== Features ===== ===== Features =====
-  * Full featured evaluation board for the [[adi>AD9680|AD9680]] and [[adi>AD9234|AD9234]]. Includes+  * Full featured evaluation board for the [[adi>AD9680|AD9680]] and [[adi>AD9234|AD9234]]. Includes
 +    * AD9680-1250EBZ
     * AD9680-1000EBZ, AD9680-LF1000EBZ     * AD9680-1000EBZ, AD9680-LF1000EBZ
     * AD9680-820EBZ, AD9680-LF820EBZ     * AD9680-820EBZ, AD9680-LF820EBZ
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     * AD9234-500EBZ, AD9234-LF500EBZ     * AD9234-500EBZ, AD9234-LF500EBZ
   * SPI interface for setup and control   * SPI interface for setup and control
-  * Wide band Balun driven input for the AD9680-1000EBZ, AD9680-820EBZ, AD9680-500EBZ, AD9234-1000EBZ and AD9234-500EBZ +  * Wide band Balun driven input for the AD9680-1250EBZ, AD9680-1000EBZ, AD9680-820EBZ, AD9680-500EBZ, AD9234-1000EBZ and AD9234-500EBZ. 
-  * Double balun input for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ and AD9234-LF500EBZ +  * Double balun input for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ and AD9234-LF500EBZ. 
-  * No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC +  * No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC. 
-  * VisualAnalog® and SPI controller software interfaces +  * VisualAnalog® and SPI controller software interfaces
-  * On-board Crystal oscillator for AD9680-LF1000EBZ, AD9234-LF1000EBZ, AD9680-500EBZ, AD9234-LF500EBZ+  * ACE (Analysis | Control | Evaluation) software interface. 
 +  * On-board Crystal oscillator for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ, AD9234-LF500EBZ
  
 ===== Helpful Documents ===== ===== Helpful Documents =====
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   * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation//   * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation//
 ===== Software Needed ===== ===== Software Needed =====
-  * [[adi>en/design-center/interactive-design-tools/visualanalog.html | VisualAnalog]] +  * [[adi>resources/tools-software/ace | ACE]] (Analysis | Control | Evaluation) or [[adi>en/design-center/interactive-design-tools/visualanalog.html | VisualAnalog]] [[adi>en/design-center/interactive-design-tools/spicontroller.html | SPIController ]] 
-  * [[adi>en/design-center/interactive-design-tools/spicontroller.html | SPIController ]]+
 ===== Design and Integration Files =====   ===== Design and Integration Files =====  
   * {{:resources:eval:ad9680:9680ce04b.zip|AD9680CE04B schematic, BOM, Gerber files}}   * {{:resources:eval:ad9680:9680ce04b.zip|AD9680CE04B schematic, BOM, Gerber files}}
   * {{:resources:eval:ad9680:9680ce02b.zip|AD9680CE02B schematic, BOM, Gerber files}}   * {{:resources:eval:ad9680:9680ce02b.zip|AD9680CE02B schematic, BOM, Gerber files}}
 +
 ===== Equipment Needed ===== ===== Equipment Needed =====
-  * Analog signal source and antialiasing filter 
-  * Sample clock source  
-  * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[adi>eval-ads7-v2|ADS7-V2EBZ]]) 
-  * PC running Windows® 
-  * USB 2.0 port 
   * [[adi>AD9680|AD9680]] or [[adi>AD9234|AD9234]] Evaluation board   * [[adi>AD9680|AD9680]] or [[adi>AD9234|AD9234]] Evaluation board
   * [[adi>eval-ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit   * [[adi>eval-ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit
 +  * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[adi>eval-ads7-v2|ADS7-V2EBZ]])
 +  * PC running Windows®
 +  * USB 2.0 High-speed A to B Cable
 +  * Low phase noise analog input source and antialiasing filter
 +  * Low phase noise sample clock source
 +  * Reference clock source
 +
 ===== Getting Started ===== ===== Getting Started =====
-This section provides quick start procedures for using the evaluation board for AD9680 or AD9234. \\+This section provides quick start procedures for using the evaluation board for AD9680 or AD9234.
  
-==== Configuring the Board ====+===== Configuring the Board =====
 Before using the software for testing, configure the evaluation board as follows:  Before using the software for testing, configure the evaluation board as follows: 
-  - Connect the evaluation board to the [[adi>eval-ads7-v2|ADS7-V2EBZ]] data capture board, as shown in Figure 2+  - Connect the evaluation board to the [[adi>eval-ads7-v2|ADS7-V2EBZ]] data capture board, as shown in Figure 5
-  - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[adi>eval-ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[adi>eval-ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. +  - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P7 on the [[adi>eval-ads7-v2|ADS7-V2EBZ]] board.  
 +  - Connect the Standard-B USB port of the [[adi>eval-ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. 
   - Turn on the [[adi>eval-ads7-v2|ADS7-V2EBZ]].    - Turn on the [[adi>eval-ads7-v2|ADS7-V2EBZ]]. 
-  - The [[adi>eval-ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager as shown in Figure 3.{{ :resources:eval:fig2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Figure 4. Device Manager showing [[adi>eval-ads7-v1|ADS7-V1EBZ]]//</WRAP> +  - The [[adi>eval-ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager as shown in Figure 6.{{ :resources:eval:fig2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Figure 6. Device Manager showing [[adi>eval-ads7-v1|ADS7-V1EBZ]]//</WRAP> 
-  - If the Device Manager does not show the [[adi>eval-ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. +  - If the Device Manager does not show the [[adi>eval-ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 6, unplug all USB devices from the PC, uninstall and re-install ACE or SPIController and VisualAnalog and restart the hardware setup from step 1. 
-  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. +  - On the ADC evaluation board, provide a clean, low jitter 1.25 GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. 
-  - On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>+  - On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP><WRAP centeralign><sub>//Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes//</sub></WRAP>
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  
-==== Visual Analog Setup ====+===== Software Setup ====
 +<WRAP indent> 
 +<WRAP><note >Note: ACE plugin is only available for AD9680 evaluation boards. Use VisualAnalog/SPIController for AD9690/AD9234 evaluation boards.</note></WRAP> 
 +<hidden ACE Setup> 
 +  - Download and install [[adi>resources/tools-software/ace>|ACE]] if it is not already installed.  
 +  - The AD9680 ACE plug-in can be found under the [[adi>en/products/ad9680.html#product-requirement|AD9680 Evaluation Board Software Section]], or through ACE's Plug-In Manager (Tools -> Manage Plug-Ins).<WRAP><note tip>Tip: Some browsers (Such as Internet Explorer) may save the file as a .zip file instead of an .acezip file. If this happens, simply download and rename the file with an .acezip file extension.</note></WRAP> 
 +  - Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install. 
 +  - Click Start -> All Programs -> Analog Devices -> ACE -> ACE 
 +  - The AD9680 plug-in should appear as in Figure 7 if installed correctly.<WRAP centeralign>{{ :resources:eval:ad9680:ace_start.jpg?direct&400 |}}//Figure 7. ACE's AD9680 Plug-in//</WRAP> 
 +  - If the AD9680 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.<WRAP><note>Note: Differences may occur between ACE plug-in versions, including the version number seen in Figure 7 above or components in any of the other images below - however, these will not affect the performance of the part, nor the fundamental features described in this user guide.</note></WRAP> 
 +  - Double click on the plug-in to open it. This will open the AD9680 Board View.<WRAP centeralign>{{ :resources:eval:ad9680:ace_board_view.jpg?direct600 |}}//Figure 8. AD9680 Board View//</WRAP><WRAP><note>Note: ACE will automatically program the FPGA (FPGA_DONE LED should be lit up) and load the default full bandwidth configuration.</note></WRAP> 
 +  - Double click on the blue AD9680 chip (in the middle of the board) to open up the Chip View.<WRAP centeralign>{{ :resources:eval:ad9680:ace_chip_view.jpg?direct&600 |}}//Figure 9. AD9680 Chip View//</WRAP> 
 +</hidden> 
 + 
 +<hidden Visual Analog & SPI Controller Setup> 
 +**Visual Analog Setup**
   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog
-  - On the VisualAnalog “New Canvas” window, click **ADC**<m>right</m>**Dual**<m>right</m>**AD9680** or **ADC**<m>right</m>**Dual**<m>right</m>**AD9234**{{ :resources:eval:fig3_selecting_canvas.png?nolink |}}<WRAP centeralign>//Figure 5. Selecting the [[adi>AD9680|AD9680]] canvas //</WRAP> +  - On the VisualAnalog “New Canvas” window, click **ADC**<m>right</m>**Dual**<m>right</m>**AD9680** or **ADC**<m>right</m>**Dual**<m>right</m>**AD9234**{{ :resources:eval:ad9680:selecting_canvas.jpg?direct&400 |}}<WRAP centeralign>//Figure 10. Selecting the [[adi>AD9680|AD9680]] canvas //</WRAP> 
-  - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 6. Programming the FPGA will provide power to the evaluation board. {{ :resources:eval:fpga_program_prompt.png?direct&300 |}}<WRAP centeralign>//Figure 6. Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP> +  - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 11. Programming the FPGA will provide power to the evaluation board.{{ :resources:eval:ad9680:programming_fpga.jpg?direct&400 |}}<WRAP centeralign>//Figure 11. Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP> 
-  - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 7){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 7. Expanding Display in VA//</WRAP> +  - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 12){{ :resources:eval:fig4_expand_display.png?direct |}}<WRAP centeralign>//Figure 12. Expanding Display in VisualAnalog//</WRAP> 
-  - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure {{ :resources:eval:fig5_change_adc_capture_settings.png?nolink&300 |}}<WRAP centeralign>//Figure 8. Changing the ADC Capture Settings//</WRAP> +  - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure 13{{ :resources:eval:fig5_change_adc_capture_settings.png?direct&200 |}}<WRAP centeralign>//Figure 13. Changing the ADC Capture Settings//</WRAP> 
-  - On the **General** tab make sure the clock frequency is set to the appropriate sample rate (eg. **1000MHz** or **500MHz**). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADs7-V2 FPGA software supports up to 2M FFT capture (1M per channel){{ :resources:eval:adc_data_capture_settings.png?direct&600 |}}<WRAP centeralign>//Figure 9. Setting the clock frequency and Capture length//</WRAP> +  - On the **General** tab make sure the clock frequency is set to the appropriate sample rate (eg. **1250 MHz or 1000 MHz**). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel){{ :resources:eval:ad9680:adc_data_capture_settings.jpg?direct&400 |}}<WRAP centeralign>//Figure 14. Setting the clock frequency and Capture length//</WRAP> 
-  - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.+  - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked.{{ :resources:eval:ad9680:adc_data_capture_device_settings.jpg?direct&400 |}}<WRAP centeralign>//Figure 15. Setting the clock frequency and capture length//</WRAP>
   - Click **OK**   - Click **OK**
-==== SPIController Setup ====+**SPI Controller Setup**
   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> SPIController <m>right</m> SPIController   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> SPIController <m>right</m> SPIController
   - Select the appropriate configuration file when prompted.   - Select the appropriate configuration file when prompted.
-  - In the **Global** tab, under the **Generic Read/Write** section, write 0x81 to register 0x000. This issues a Soft reset for the DUT. {{ :resources:eval:spi_soft_reset.png?600 |}}<WRAP centeralign>//Figure 10. Sending a Soft Reset to the AD9680//</WRAP> +  - In the **Global** tab, under the **Generic Read/Write** section, write **0x81** to register **0x000**. This issues a **Soft Reset** for the DUT or just click **Reset** at **CHIP PORT CFG(0)**.{{ :resources:eval:ad9680:spi_soft_reset.jpg?direct&600 |}}<WRAP centeralign>//Figure 16. Sending a Soft Reset to the AD9680//</WRAP> 
-  - Individual Channel control for **ADC A** and **ADC B** are done using the **Device Index Register (0x008)** in the Global tab.{{ :resources:eval:fig10_devindex.png?400 |}}<WRAP centeralign>//Figure 11. Device Index for ADC Channel A and Channel B//</WRAP>+  - Individual Channel control for **ADC A** and **ADC B** are done using the **Device Index Register (0x008)** in the Global tab.{{ :resources:eval:ad9680:spi_device_index.jpg?direct&600 |}}<WRAP centeralign>//Figure 17. Device Index for ADC Channel A and Channel B//</WRAP>
   - Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:     - Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:  
-    - **Chip Configuration Register (0x002)**: This option allows the channel to be powered on +    - **Chip Configuration Register (0x002)**: This option allows the channel to be powered on.
     - **Buffer Current Setting (0x018)**: This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between I<sub>AVDD3</sub> and Buffer Current Setting.      - **Buffer Current Setting (0x018)**: This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between I<sub>AVDD3</sub> and Buffer Current Setting. 
     - **Analog Input Differential Termination (0x016)**: This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced.      - **Analog Input Differential Termination (0x016)**: This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced. 
-    - **Input Full Scale Range (0x025)**: At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.+    - **Input Full Scale Range (0x025)**: At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.{{ :resources:eval:ad9680:spi_adc_a.jpg?direct&600 |}}<WRAP centeralign>//Figure 18. SPI Controller Channel A and B Options//</WRAP> 
 +</hidden> 
 +</WRAP> 
 ===== Sample Configuration 1: Full Bandwidth Mode ===== ===== Sample Configuration 1: Full Bandwidth Mode =====
-  - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register** address 0x200 to **Full Bandwidth Mode** and **Chip Decimation Ratio Control Register** 0x201 to **Full Sample Rate**.{{ :resources:eval:ad9680_fbw_chip.png?300 |}}<WRAP centeralign>//Figure 12. Setting Chip Mode Control and Decimation Ratio Registers//</WRAP> +<WRAP indent> 
-  - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ :resources:eval:ad9680_jesd_571.png?400 |}}<WRAP centeralign>//Figure 13. JESD204B Serial Transmit Power Down//</WRAP> +<hidden ACE Configuration> 
-  - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/resources/eval/ad9680-1000ebz#configuring_the_board|Configuring the Board]] section.{{ :resources:eval:fig8_lane_rate_ctrl.png?nolink |}}<WRAP centeralign>//Figure 14. Setting the JESD204B Lane Rate//</WRAP> +  - Under **Initial Configuration** at board view, set the clock input to 1250 MHz. Change the **Clock Divide Ratio** to divide by 1. Change the **Chip Operation Mode** to full bandwidth mode. Change the number of **Lane** to 4. Change the number of **Virtual Converter** to 2. Change the number of **Octets per Frame** to 1. Click **Apply** to apply the chip settings. Set the reference clock to 625 MHz to match these settings.{{ :resources:eval:ad9680:ace_chip_settings.jpg?direct&200 |}}<WRAP centeralign>//Figure 19. Chip Settings//</WRAP><WRAP><note>Note: ACE will automatically load the default full bandwidth configuration and can skip to step 7 to proceed to **Analysis** tab to capture data.</note></WRAP> 
-  - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **NO** DDCs (//Full Bandwidth Mode//), the values for **L.M.F** are **4.2.1**{{ :resources:eval:ad9680_jesd_570.png?300 |}}<WRAP centeralign>//Figure 15. Setting the JESD204B Quick Configuration Register//</WRAP> +  - The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the **Read All button**.{{ :resources:eval:ad9680:ace_read_all.jpg?direct&600 |}}<WRAP centeralign>//Figure 20. Read All Button//</WRAP> 
-  - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ :resources:eval:ad9680_jesd_adcbase4.png?600 |}}<WRAP centeralign>//Figure 16. Reading the JESD204B Configuration Registers//</WRAP> +  - Set the **PLL Control** serial lane rate to 6.25 Gbps to 12.5 Gbps and click **Apply Changes**. The decision to use Maximum Lane Rate (6.25 Gbps to 12.5 Gbps) or Low Lane Rate (3.125 Gbps to 6.25 Gbps) should be based on the **Lane Line Rate** that was calculated in [[/resources/eval/ad9680-1000ebz#configuring_the_board|Configuring the Board]] section.{{ :resources:eval:ad9680:ace_pll_control.jpg?direct&600 |}}<WRAP centeralign>//Figure 21. PLL Control//</WRAP> 
-  - On address **0x58F**, change the Converter Resolution to **14** for AD9680 (12 for AD9234). +  - Issue a **Data Path Reset** to the AD9680 by clicking its checkbox and clicking **Apply Changes**. The data path reset bit will automatically self clear.{{ :resources:eval:ad9680:ace_data_path_reset.jpg?direct&600 |}}<WRAP centeralign>//Figure 22. Data Path Reset//</WRAP> 
-  - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). +  - If the **PLL Locked** indicator lights up, you can reset it by powering down the JESD link using the **Link Control** dropdown box, and clicking **Apply Changes**.{{ :resources:eval:ad9680:ace_link_control.jpg?direct&600 |}}<WRAP centeralign>//Figure 23. PLL Lock, Link Power Down//</WRAP> 
-  - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a "1" to denote a lock. {{ :resources:eval:ad9680_jesd_pll.png?400 |}}<WRAP centeralign>//Figure 17. Reading the PLL Status Register//</WRAP> +  - Enable the **Link Control** again and **Apply Changes**.{{ :resources:eval:ad9680:ace_link_enable.jpg?direct&600 |}}<WRAP centeralign>//Figure 24. PLL Lock,  Link Enable//</WRAP> 
-==== Obtaining an FFT ==== +  - Click **Apply** at **AD9680 Configuration** and then **Proceed to Analysis**. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on **FFT** and **Run Once** to capture once.{{ :resources:eval:ad9680:ace_proceed_to_analysis.jpg?direct&600 |}}<WRAP centeralign>//Figure 25. Analysis Tool//</WRAP>{{ :resources:eval:ad9680:ace_analysis.jpg?direct&600 |}}<WRAP centeralign>//Figure 26. Display FFTs and Run once//</WRAP><WRAP><note tip>Tip: Capturing data using another program (e.g. VisualAnalog, proprietary code, etc.) while using ACE concurrently may cause errors in ACE's data capture. If this occurs, the best solution is to restart the evaluation boards and work solely via ACE, or to setup the part in ACE then capture solely in the other program.</note></WRAP> 
-  - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 18.{{ :resources:eval:fig12_cha172mhz_17p68dbm_2xibuff.png?nolink |}}<WRAP centeralign>//Figure 18. AD9680-1000 FFT at 170MHz Analog Input//</WRAP> +  - **Channel A** and **Channel B** can be selected individually to display their **FFTs**.{{ :resources:eval:ad9680:ace_channel.jpg?direct&600 |}}<WRAP centeralign>//Figure 27. Channel Selection//</WRAP> 
-  - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) +  - A successful capture is shown below, with a filtered 170 MHz signal inputted at on Channel A.{{ :resources:eval:ad9680:ace_ch_a.jpg?direct&600 |}}<WRAP centeralign>//Figure 28. Example Input to Channel A//</WRAP> 
-  - To save the FFT plot do the following +  - To save the FFT plot, click on **Export** button at **Analysis Results** tab and save it to a location of choice. 
-  - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 19. Floating the FFT window//</WRAP> +</hidden> 
-  - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:fig14_savingfft.png?nolink |}}<WRAP centeralign>//Figure 20. Saving the FFT//</WRAP>+ 
 +<hidden Visual Analog & SPI Controller Configuration> 
 +**SPI Controller Configuration** 
 +  - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register** address 0x200 to **Full Bandwidth Mode** and **Chip Decimation Ratio Control Register** 0x201 to **Full Sample Rate**.{{ :resources:eval:ad9680_fbw_chip.png?300 |}}<WRAP centeralign>//Figure 29. Setting Chip Mode Control and Decimation Ratio Registers//</WRAP> 
 +  - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ :resources:eval:ad9680_jesd_571.png?400 |}}<WRAP centeralign>//Figure 30. JESD204B Serial Transmit Power Down//</WRAP> 
 +  - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/resources/eval/ad9680-1000ebz#configuring_the_board|Configuring the Board]] section.{{ :resources:eval:fig8_lane_rate_ctrl.png?direct |}}<WRAP centeralign>//Figure 31. Setting the JESD204B Lane Rate//</WRAP> 
 +  - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **NO** DDCs (//Full Bandwidth Mode//), the values for **L.M.F** are **4.2.1**{{ :resources:eval:ad9680_jesd_570.png?300 |}}<WRAP centeralign>//Figure 32. Setting the JESD204B Quick Configuration Register//</WRAP> 
 +  - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ :resources:eval:ad9680_jesd_adcbase4.png?600 |}}<WRAP centeralign>//Figure 33. Reading the JESD204B Configuration Registers//</WRAP> 
 +  - On address **0x58F** (see figure 33), change the Converter Resolution to **14** for AD9680 (12 for AD9234). 
 +  - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571), see figure 30
 +  - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a "1" to denote a lock. {{ :resources:eval:ad9680_jesd_pll.png?200 |}}<WRAP centeralign>//Figure 34. Reading the PLL Status Register//</WRAP> 
 +**Obtaining an FFT on Visual Analog** 
 +  - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 35.{{ :resources:eval:ad9680:va_ch_a.jpg?direct&600 |}}<WRAP centeralign>//Figure 35. AD9680-1250 FFT at 170MHz Analog Input//</WRAP> 
 +  - Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window. 
 +  - To save the FFT plot do the following: 
 +    - Click on the **Float Form button** in the FFT window.{{ :resources:eval:fig13_floatform.png?direct |}}<WRAP centeralign>//Figure 36. Floating the FFT window//</WRAP> 
 +    - Click on **File <m>right</m> Save Form As** button and save it to a location of choice.{{ :resources:eval:fig14_savingfft.png?direct |}}<WRAP centeralign>//Figure 37. Saving the FFT//</WRAP> 
 +</hidden> 
 +</WRAP>
  
 ===== Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4 ===== ===== Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4 =====
-  In the VisualAnalog Setup, follow Steps 1-5 and after that, click the **ADC Data Capture Settings**, remove **Ch.A and Ch.B** output data, and add **Ch. DDC0 and Ch. DDC1** output data.{{ :resources:eval:ad9680_ddc_va_2ddcs.png?600 |}}<WRAP centeralign>//Figure 21VisualAnalog ADC Data Capture Settings for DDC//</WRAP> +<WRAP indent> 
-  In the SPIController Setup, follow Steps 1-4. +<hidden ACE Configuration> 
-  - Set the ADC Configuration Registers in **ADCBase0** tab. Write **Chip Mode Control Register (0x200)** to **Two Digital Down Converters** and **Chip Decimation Ratio Control Register (0x201)** to **Decimate by 4**.{{ :resources:eval:ad9680_ddc_chip_mode.png?300 |}}<WRAP centeralign>//Figure 22Setting Chip Mode Control and Decimation Ratio Registers//</WRAP> +  Under **Initial Configuration** at board view, set the clock input to 1250 MHz. Change the **Clock Divide Ratio** to divide by 1. Change the **Chip Operating Mode** for two DDCs. The DDC settings will become availableset the **Decimation Ratio** select "HB1_HB2 Complex" - two half-band filters, and set the **Output Select** select complexi.eDecimate-by-4. Set the number of **Lanes** to 2, the number of **Virtual Converters** to 4, and the number of **Octets per Frame** to 4. Click **Apply** to apply the settings. Set the reference clock to 625 MHz to match these settings.{{ :resources:eval:ad9680:ace_ddc_chip_setting.jpg?direct&200 |}}<WRAP centeralign>//Figure 38DDC Chip Settings//</WRAP> 
-  - For DDC settings, proceed to **ADCBase1** tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of **0x310** and **0x330**, respectively, to **Real Mixer, Variable IF Mode, Complex (I/Q) Decimate by 4**Channel Input Selection for address **0x311** is set to **Channel A** for I and Q while address **0x331** is set to **Channel B** for I and Q. {{ :resources:eval:ad9680_ddc_setting.png?600 |}}<WRAP centeralign>//Figure 23DDC Control Registers//</WRAP> +  - The **Chip View** will update to reflect the changesClick on the **NCO block** to change the Numerically Controlled Oscillator's frequency to 175 MHz.{{ :resources:eval:ad9680:ace_ddc_nco_freq.jpg?direct&600 |}}<WRAP centeralign>//Figure 39NCO Frequency Setting//</WRAP> 
-  - For frequency tuning word (FTW), addresses **0x314-315** are set as required by application for DDC0, and addresses **0x334-335** are set as required by application for DDC1. Figure xx below shows the calculation for NCO Frequency Tuning Word. {{ :resources:eval:ad9680_ddc_ftw_setting.png?600 |}}<WRAP centeralign>//Figure 24Frequency Tuning Word Formula//</WRAP> +  - Enable the 6dB gain for the DDC at the amplifier block drop down menu.{{ :resources:eval:ad9680:ace_ddc_gain.jpg?direct&600 |}}<WRAP centeralign>//Figure 40DDC Gain//</WRAP> 
-  - After setting all DDC registers, go to **Generic Write/Read** in **Global** tab and write **0x10** to address **0x300 (DDC soft reset)**, and write back to **0x00 (DDC normal operation)**. Same process can be done by checking and unchecking the **DDC Soft Reset** box. {{ :resources:eval:ad9680_ddc_soft_reset.png?300 |}}<WRAP centeralign>//Figure 25. DDC Synchronization Control Register//</WRAP> +  - Set the **Mixer** to Real. Click **Apply Changes** to apply configuration at **DDC0**.{{ :resources:eval:ad9680:ace_ddc_real_mixer.jpg?direct&600 |}}<WRAP centeralign>//Figure 41. DDC Mixer//</WRAP> 
-  - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ :resources:eval:ad9680_jesd_571.png?400 |}}<WRAP centeralign>//Figure 26JESD204B Serial Transmit Power Down//</WRAP> +  - Navigate to the second DDC (**DDC1**) and make the same changes.{{ :resources:eval:ad9680:ace_ddc_1.jpg?direct&600 |}}<WRAP centeralign>//Figure 42DDC Selection//</WRAP> 
-  - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/resources/eval/ad9680-1000ebz#configuring_the_board|Configuring the Board]] section.{{ :resources:eval:fig8_lane_rate_ctrl.png?nolink |}}<WRAP centeralign>//Figure 27Setting the JESD204B Lane Rate//</WRAP> +  - Set the **DDC Soft Reset** to **DDC Held in Reset** in dropdown menu to soft reset the DDC, and click **Apply Changes**.{{ :resources:eval:ad9680:ace_ddc_soft_reset.jpg?direct&600 |}}<WRAP centeralign>//Figure 43DDC Soft Reset//</WRAP><WRAP centeralign><note>Note: Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations.</note></WRAP> 
-  - Set the **JESD204B Quick Configuration register (0x570)**. For 1000MSPS operation with **2** DDCs (//Two Digital Down Converters//)the values for **L.M.F** are **2.4.4**.{{ :resources:eval:ad9680_ddc_jesd_570.png?300 |}}<WRAP centeralign>//Figure 28. Setting the JESD204B Quick Configuration Register//</WRAP> +  - Change the **DDC Soft Reset** to **Normal Operation** in dropdown menuand click **Apply Changes**. And then click on **Proceed to Analysis**.{{ :resources:eval:ad9680:ace_ddc_soft_reset_enable.jpg?direct&600 |}}<WRAP centeralign>//Figure 44DDC Soft Reset - Normal Operation//</WRAP> 
-  - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.{{ :resources:eval:ad9680_ddc_jesd_quick_config.png?600 |}}<WRAP centeralign>//Figure 29Reading the JESD204B Configuration Registers//</WRAP> +  - In **Analysis** toolrun a capture onceDDC0 can be selected from Channel A and DDC1 can be selected from Channel B (see figure 45). 
-  - On address **0x58F**, change the Converter Resolution to **14** for AD9680 (12 for AD9234). +  - A successful capture is shown belowwith a filtered 170 MHz signal inputted on **Channel A / DDC0**.{{ :resources:eval:ad9680:ace_ddc_a.jpg?direct&600 |}}<WRAP centeralign>//Figure 45Example Input to DDC0//</WRAP
-  - Back to **ADCBase3** tab, uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). +</hidden>
-  - After the quick configuration setting is completedthe **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a "1" to denote a lock. {{ :resources:eval:ad9680_jesd_pll.png?400 |}}<WRAP centeralign>//Figure 30Reading the PLL Status Register//</WRAP>+
  
-==== Obtaining an FFT ==== +<hidden Visual Analog & SPI Controller Configuration> 
-  - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 31.{{ :resources:eval:ad9680_ddc_fft.png?nolink |}}<WRAP centeralign>//Figure 31. AD9680-1000 FFT at 150.3MHz Analog Input, NCO_FTW = 155MHz//</WRAP>+**Visual Analog & SPI Controller Configuration** 
 +  - In the [[/resources/eval/ad9680-1000ebz#software_setup|Visual Analog Software Setup]], follow Steps 1-5 and after that, click the **ADC Data Capture Settings**, remove **Ch.A and Ch.B** output data, and add **Ch. DDC0 and Ch. DDC1** output data.{{ :resources:eval:ad9680_ddc_va_2ddcs.png?600 |}}<WRAP centeralign>//Figure 46. VisualAnalog ADC Data Capture Settings for DDC//</WRAP> 
 +  - In the [[/resources/eval/ad9680-1000ebz#software_setup|SPI Controller Software Setup]], follow Steps 1-4. Set the **ADC Configuration Registers** in **ADCBase0** tab. Write **Chip Mode Control Register (0x200)** to **Two Digital Down Converters** and **Chip Decimation Ratio Control Register (0x201)** to **Decimate by 4**.{{ :resources:eval:ad9680_ddc_chip_mode.png?300 |}}<WRAP centeralign>//Figure 47. Setting Chip Mode Control and Decimation Ratio Registers//</WRAP> 
 +  - For **DDC Settings**, proceed to **ADCBase1** tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of **0x310** and **0x330**, respectively, to **Real Mixer, Variable IF Mode, Complex (I/Q) Decimate by 4**. Channel Input Selection for address **0x311** is set to **Channel A** for I and Q while address **0x331** is set to **Channel B** for I and Q.{{ :resources:eval:ad9680_ddc_setting.png?600 |}}<WRAP centeralign>//Figure 48. DDC Control Registers//</WRAP> 
 +  - For frequency tuning word (FTW), addresses **0x314-315** are set as required by application for DDC0, and addresses **0x334-335** are set as required by application for DDC1. Figure 49 below shows the calculation for NCO Frequency Tuning Word. {{ :resources:eval:ad9680_ddc_ftw_setting.png?600 |}}<WRAP centeralign>//Figure 49. Frequency Tuning Word Formula//</WRAP> 
 +  - After setting all DDC registers, go to **Generic Write/Read** in **Global** tab and write **0x10** to address **0x300 (DDC soft reset)**, and write back to **0x00 (DDC normal operation)**. Same process can be done by checking and unchecking the **DDC Soft Reset** box. {{ :resources:eval:ad9680_ddc_soft_reset.png?300 |}}<WRAP centeralign>//Figure 50. DDC Synchronization Control Register//</WRAP> 
 +  - For JESD204B setting, proceed to **ADCBase3** tab. Check the **Serial Transmit Power Down** box in **JESD204B Link Control Register (0x571)**.{{ :resources:eval:ad9680_jesd_571.png?400 |}}<WRAP centeralign>//Figure 51. JESD204B Serial Transmit Power Down//</WRAP> 
 +  - Set the Lane Rate setting register 0x56E to **Maximum Lane Rate**. The decision to use **Maximum Lane Rate** mode or **Low Lane Rate** mode should be based on the Lane Line Rate that was calculated in [[/resources/eval/ad9680-1000ebz#configuring_the_board|Configuring the Board]] section.{{ :resources:eval:fig8_lane_rate_ctrl.png?direct |}}<WRAP centeralign>//Figure 52. Setting the JESD204B Lane Rate//</WRAP> 
 +  - Set the **JESD204B Quick Configuration register (0x570)**. For 1000 MSPS operation with **2** DDCs (//Two Digital Down Converters//), the values for **L.M.F** are **2.4.4**.{{ :resources:eval:ad9680_ddc_jesd_570.png?300 |}}<WRAP centeralign>//Figure 53. Setting the JESD204B Quick Configuration Register//</WRAP> 
 +  - Proceed to **ADCBase4** tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on **ADCBase3** tab are reflected.{{ :resources:eval:ad9680_ddc_jesd_quick_config.png?600 |}}<WRAP centeralign>//Figure 54. Reading the JESD204B Configuration Registers//</WRAP> 
 +  - On address **0x58F** (see figure 54), change the Converter Resolution to **14** for AD9680 (12 for AD9234). 
 +  - Back to **ADCBase3** tab (se figure 51), uncheck the **Serial Transmit Power Down** box in JESD204B Link Control Register (0x571). 
 +  - After the quick configuration setting is completed, the **PLL Lock Detect register 0x56F** will read **0x80** to denote a lock. The SPIController interface will show a "1" to denote a lock. {{ :resources:eval:ad9680_jesd_pll.png?400 |}}<WRAP centeralign>//Figure 55. Reading the PLL Status Register//</WRAP> 
 +**Obtaining an FFT on Visual Analog** 
 +  - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 56.{{ :resources:eval:ad9680_ddc_fft.png?direct |}}<WRAP centeralign>//Figure 56. AD9680-1000 FFT at 150.3MHz Analog Input, NCO_FTW = 155MHz//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.)   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.)
 +</hidden>
 +</WRAP>
 +
 ===== Validating Deterministic Latency Using Subclass 1 Operation ===== ===== Validating Deterministic Latency Using Subclass 1 Operation =====
 The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency  differences between subclass 0 and subclass 1 operation.  The "Validating Subclass 1 Operation of the AD9680" document will guide the user through the necessary steps to perform this validation.  SPI Controller scripts for several full bandwidth modes are included for convenience. The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency  differences between subclass 0 and subclass 1 operation.  The "Validating Subclass 1 Operation of the AD9680" document will guide the user through the necessary steps to perform this validation.  SPI Controller scripts for several full bandwidth modes are included for convenience.
-{{:resources:eval:ad9680_ads7v2_dl_demo.zip|}} +  *{{:resources:eval:ad9680_ads7v2_dl_demo.zip|}} 
-{{:resources:eval:spicontroller_scripts_for_dl_demo.zip|}} +  *{{:resources:eval:spicontroller_scripts_for_dl_demo.zip|}}
  
 ===== Troubleshooting Tips ===== ===== Troubleshooting Tips =====
 +** Evaluation board is not functioning properly **
 +  * It is possible that a board component has been rendered inoperable by ESD, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows:
 +  *<WRAP>
 +^  Domain  ^  Test Point  ^  Approx. Voltage  ^
 +|  AVDD_1    |  TP406  |  1.25 V  |
 +|  AVDD_1    |  TP106  |  1.25 V  |
 +|  AVDD_2    |  TP404  |  2.50 V  |
 +|  AVDD_1P8  |  TP401  |  1.80 V  |
 +|  DVDD      |  TP407  |  1.25 V  |
 +|  DRVDD      TP410  |  1.25 V  |
 +</WRAP>
 +  * If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F400 or F401, a component may have been damaged.
 +
 +** Evaluation board is not communicating with the ADS7-V2 / No SPI communication **
 +  * Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (**FPGA_DONE**) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed.
 +  * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts.
 +  * To test SPI operation, attempt to both read and write to register 0x00A (Scratch Pad) using ACE's Register Debugger (Tools -> Register Debugger). This register is an open register available for testing memory reads and writes. If the register reads back the same value written to it, SPI is operational. 
 +  * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.
 +  * Register 0x000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed. 
 +
 +** ACE software fails to capture date **
 +  * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.
 +  * Check the Clock Status register 0x011C to see if the input sample clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator input on connector J801. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip.
 +  * Check the PLL Locked indicator (see figure 23) or register 0x056F (PLL Status). If the light in the plugin chip view is green or if the register reads back 0x80, the PLL is locked. If it is not locked:
 +    * Check the clock being input to connector J801 (in this guide, 1.25 GHz or 1 GHz depending on the evaluation board).
 +    * Check the JESD204B settings under the Initial Configuration. Reference the [[adi>AD9680|AD9680]] / [[adi>AD9690|AD9690]] / [[adi>AD9234|AD9234]] datasheet for supported lane options.
 +    * Check the Reference Clock and make sure it matches your JESD settings.
 +    * Make sure P100 (Power Down / Standby Jumper) is not jumped.
 +
 +** VisualAnalog displays a blank FFT when the RUN button is clicked **
 +  * Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 57.{{ :resources:eval:fig17_clockdetect.png?direct |}}<WRAP centeralign>//Figure 57. Clock Detection Status Register//</WRAP>
 +  * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController (see figure 34 or 55).
 + 
 +** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" **
 +  * Make sure all power and USB connections are secure.
 +  * Make sure that the Reference Clock is ON and set to the appropriate frequency.
 +  
 ** FFT plot appears abnormal ** ** FFT plot appears abnormal **
   * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.    * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. 
-  * In VisualAnalog, Click on the Settings button in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos compliment by default). Repeat for the other channel. +  * In ACE Analysis tab under CAPTURE -> General -> Encoding (see figure 26), check that the encoding is set to correct number format (two's compliment by default). 
-  * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 32{{ :resources:eval:fig15_datapathsoftreset.png?nolink |}}<WRAP centeralign>//Figure 32. Issuing a data path soft reset through SPIController//</WRAP>+    * Issue a Data Path Reset through ACE Chip View (see figure 22). 
 +  * In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel. 
 +    * Issue a Data Path Soft Reset through SPIController Global tab (see Figure 23).
  
 ** The FFT plot appears normal, but performance is poor. ** ** The FFT plot appears normal, but performance is poor. **
Line 153: Line 250:
   * Make sure the signal generators for the clock and the analog input are clean (low phase noise).   * Make sure the signal generators for the clock and the analog input are clean (low phase noise).
   * If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.   * If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
-  * Make sure the SPI config file matches the product being evaluated.+  * Make sure the SPIController config file matches the product being evaluated when using the VisualAnalog.
  
 ** The FFT window remains blank after the Run button is clicked ** ** The FFT window remains blank after the Run button is clicked **
   * Make sure the evaluation board is securely connected to the [[adi>eval-ads7-v2|ADS7-V2]].   * Make sure the evaluation board is securely connected to the [[adi>eval-ads7-v2|ADS7-V2]].
-  * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the [[adi>eval-ads7-v2|ADS7-V2]].  If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the [[adi>eval-ads7-v2|ADS7-V2]] setup process. +  * Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the [[adi>eval-ads7-v2|ADS7-V2]].  If this LED is not illuminated restart the ACE software to reload the FPGA program, or reprogram the FPGA through VisualAnalog if not using the ACE software. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the [[adi>eval-ads7-v2|ADS7-V2]] setup process. 
-  * Make sure the correct FPGA //bin// file was used to program the FPGA. +    * Make sure the correct FPGA //bin// file was used to program the FPGA in VisualAnalog
-  * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, and verify that the **Clock Frequency** is properly set.{{ :resources:eval:fig6_adc_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 33. Setting the correct clock frequeency in VisualAnalog//</WRAP> +  * Be sure that the correct sample rate is programmed. 
-  * Ensure that the REFCLOCK is ON and set to the appropriate frequency. +    * In ACE, check the Board view tab and Chip view tab if the Sampling Frequency is properly set (see figures 8 & 9) 
-  * Restart SPIController. +    * In VisualAnalog, click on the Settings button in the ADC Data Capture block. Verify that the Clock Frequency is properly set (see figure 14)
- +  * Ensure that the Reference Clock is ON and set to the appropriate frequency. 
-** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" ** +  * Restart ACE software or VisualAnalog/SPIController.
-  * Make sure all power and USB connections are secure. +
-  * Make sure that the REFCLOCK is ON and set to the appropriate frequency. +
- +
-** VisualAnalog displays a blank FFT when the RUN button is clicked ** +
-  * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 34.{{ :resources:eval:fig17_clockdetect.png?nolink |}}<WRAP centeralign>//Figure 34. Clock Detection Status Register//</WRAP> +
-  * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController.+
resources/eval/ad9680-1000ebz.txt · Last modified: 05 Feb 2024 03:49 by Deferson Romero