This user guide describes the AD9656 evaluation board AD9656EBZ, which provides the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the device is also described.
The AD9656 data sheet provides additional information and should be consulted when using the evaluation board. Documents and software tools are available at AD9656 and www.analog.com/hsadcevalboard. For additional information or questions, send an email to firstname.lastname@example.org.
This section provides quick start procedures for using the AD9656EBZ board. Both the default and optional ADC settings are described.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9656 in its various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See Schematics, layout files, bill of materials for schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
The AD9656EBZ can obtain its power from the HSC-ADC-EVALEZ through the FMC connector. P101 and P103 both need to have pin 1 tied to pin 2 for obtaining board power through the FMC connector from the HSC-ADC-EVALEZ capture board. If P101 and P103 have pin 1 jumpered to pin 2, do not connect the supplied 6V wall supply to the AD9656 evaluation board. When changing the configuration of P101 and P103, please remove both jumpers and then place them in their desired positions.
Alternatively, the AD9656EBZ can obtain its power from the wall-mountable 6V, 2A switching power supply. For this mode, P101 and P103 both need to have pin 2 tied to pin 3. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P102. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.
Also, the evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E104, E105, E106, and E108 ferrite beads to disconnect the on-board LDOs from the power planes. Note that in some board configurations some of these might already be uninstalled. P104 and P105 headers can be installed to facilitate connection of external bench supplies to the board. E110, E111, E112 and E113 need to be populated to connect P104 and P105 to the board power domains. A 1.8V , 0.5A supply is needed for 1.8V_DUT_AVDD, 1.8V_DRVDD and 1.8V_DVDD. Although the voltage requirements are the same for these three, it is recommended that separate supplies be used for each of these.
A 3.3V, 0.5A supply is needed for 3.3V_DIG, which is used to power additional on board circuitry.
The four channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50Ω impedance. When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters as close to the evaluation board as possible.
The default clock input circuit is derived from an on-board 125MHz crystal oscillator feeding through a transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T302) that adds negligible jitter to the clock path. The external clock input (J302) is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR301 before entering the ADC clock inputs. The AD9656 ADC is equipped with an internal clock divider (programmable divide ratios of 1 through 8) to facilitate usage with higher frequency clocks. When using the internal divider and a higher input clock frequency, remove CR301 to preserve the slew rate of the clock signal.
The AD9656EBZ board is set up to be clocked through the transformer-coupled input network from the 125MHz crystal oscillator, Y801. If an external clock source is desired, remove C302 (optionally) and Jumper J304 to disable the oscillator from running and connect the external clock source to the SMA connector, J302 (labeled CLOCK+).
If an external clock source is used instead of the onboard crystal oscillator, it should also be supplied with a clean signal generator as previously specified for the analog input signals. Analog Devices evaluation boards typically can accept ~2.8V p-p or 13 dBm sine wave input for the clock at the board SMA clock connector.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALEZ) for data capture. The JESD204B outputs from the ADC are routed to P2 using 100Ω differential traces. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.
|P101, P103||These jumpers determine the power source for the AD9656EBZ.
Connect Pin 1 to Pin 2 on both P101 and P103 to power the ADC board from the HSC-ADC-EVALEZ through the FMC connector.
Connect Pin 2 to Pin 3 on both P101 and P103 to power the ADC board from the wall supply connected to P102.
Leave both P101 and P103 unjumpered if using headers P104 and P105.
|J304||This jumper enables the on-board crystal oscillator. Remove this jumper (and optimally C302) if an external off-board clock source is used.|
|J206||This jumper selects between internal VREF and external VREF.
To choose the ADC's internal reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND) as shown in Figure 2.
Please see Note regarding Figure 3 before proceeding.
The default value of the internal reference is 1 V. SPI Register 0x18 Bits[7:6] can be used to program the internal reference voltage to values from 1 V to 1.4 V, in 0.1 V increments. Register control is accomplished with SPIController software, which is discussed below in the Setting up the SPI Controller Software section.
To use the on-board AD822 buffered reference, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF). Adjust external VREF to the desired value (from 1.0 V to 1.4 V) using potentiometer R247.
To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9656 reference voltage is specified to be from 1.0 V to 1.4 V.
Figure 2. Default Jumper Connections for AD9656EBZ Board
Figure 3. Silkscreen error on 9656CE01C board -- See note below.
Note: The correct numbering is shown in the green box in Figure 3.
The installers for VisualAnalog and SPIController are in the following locations:
Run these installers on the PC that is connected to the evaluation setup before proceeding.
After configuring the board hardware, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 5. VisualAnalog Window Toolbar, Collapsed Display
Figure 6. VisualAnalog, Main Window Expanded Display
4. To configure VisualAnalog to operate with the AD9656, push the Settings button on the ADCDataCapture block, as shown in Figure 7.
Figure 7. VisualAnalog ADC Data Capture Block
5. In the ADC Data Capture Settings Window, General Tab, select AD9656 to be the device, enter the sample clock frequency (125 is the default value), as shown in Figure 8. The sample frequency entered here is used for scaling of frequency values in test results and graphs. In the Output Data field, the channels to be tested are selected, as well as the FFT capture depth (“Length”). Note that the total of the capture depths for all selected channels cannot exceed 256k.
Figure 8. VisualAnalog ADC Data Capture Settings Window, General Tab
6. In the ADC Data Capture Settings Window, Capture Board Tab, enter 60 in the Fill Delay field. Push the Browse button to navigate to the FPGA program file for the AD9656. The default installation location and filename will be similar to: C:\Program Files\Analog Devices\VisualAnalog\Hardware\HADv6\AD9656_hadv6fmc.mcs
Push the program button.
Figure 9. VisualAnalog ADC Data Capture Settings Window, Capture Board Tab
7. In the ADC Data Capture Settings Window, Device Tab, check the Enable Data Capture Controls checkbox. The capture control fields will be enabled.
Though the AD9656 supports a wide variety of converter/lane/sample rate configurations, the software supports only the configurations in the software menu as an out-of-the-box functional kit. If other sample rates or configurations are required, an additional external clock is likely needed.
Figure 10. VisualAnalog ADC Data Capture Settings Window, Device Tab
8. VisualAnalog is now setup to work with the AD9656EBZ in the default configuration. Other VisualAnalog features and capture settings are documented in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual.
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 11. SPI Controller, CHIP ID(1) Box
Figure 12. SPI Controller, New DUT Button
Figure 13. SPI Controller, CLOCK DIVIDE(B) Box
Figure 14. SPI Controller, Chip Power Mode - Digital Reset Selection
Figure 15. SPI Controller, Quick Configure Box
Figure 16. SPI Controller, Example ADC A Page
Figure 17. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 18. Graph Window of VisualAnalog
Lack of SPI communication will cause difficulty in configuring the ADC.
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run in VisualAnalog (see Figure 17) is clicked, do the following: