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| resources:eval:ad9576-user-guide [06 Sep 2016 13:49] – [Online Resources] Neil Weeks | resources:eval:ad9576-user-guide [03 Jan 2021 22:12] – fix links Robin Getz | ||
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| Required Software | Required Software | ||
| * [[resources: | * [[resources: | ||
| - | * [[http:// | + | * [[adi>media/ |
| Documents Needed | Documents Needed | ||
| - | * [[http:// | + | * [[adi>static/ |
| * [[http:// | * [[http:// | ||
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| The AD9576 evaluation board is a compact, easy-to-use platform for evaluating all features of the [[adi> | The AD9576 evaluation board is a compact, easy-to-use platform for evaluating all features of the [[adi> | ||
| - | The [[adi> | + | The [[adi> |
| <WRAP centeralign> | <WRAP centeralign> | ||
| {{ : | {{ : | ||
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| ^ P208 | P210 | P212 | | ^ P208 | P210 | P212 | | ||
| - | **Please note:** Each AD9576 input receiver should be configured appropriately for signal applied. Please see the Reference Input section and Table 32 of the [[http:// | + | **Please note:** Each AD9576 input receiver should be configured appropriately for signal applied. Please see the Reference Input section and Table 32 of the [[adi>static/ |
| ==== Serial Port Configuration Pins ==== | ==== Serial Port Configuration Pins ==== | ||
| The logic state of the AD9576 serial port configuration pins, SP0 and SP1, are read upon exit from a reset state and determine the protocol of the serial port as well as if a PPR load will be executed. P102 and P103 are connected to SP0 and SP1 respectively and **Table 4** shows the effect of P102 and P103 states at release from a reset state.\\ | The logic state of the AD9576 serial port configuration pins, SP0 and SP1, are read upon exit from a reset state and determine the protocol of the serial port as well as if a PPR load will be executed. P102 and P103 are connected to SP0 and SP1 respectively and **Table 4** shows the effect of P102 and P103 states at release from a reset state.\\ | ||
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| ^ P404 | P408 | P412 | P416 | | ^ P404 | P408 | P412 | P416 | | ||
| - | Used in conjunction with the PPR tables (Table 31 - Table 34) in the [[http:// | + | Used in conjunction with the PPR tables (Table 31 - Table 34) in the [[adi>media/ |
| **Please note:** The AD9576 input receivers physical connections should be configured to match the reference input format configured by PPR0 and the AD9576 outputs should be terminated to match the output logic formats determined by PPR1, PPR2, and PPR3.\\ | **Please note:** The AD9576 input receivers physical connections should be configured to match the reference input format configured by PPR0 and the AD9576 outputs should be terminated to match the output logic formats determined by PPR1, PPR2, and PPR3.\\ | ||
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| </ | </ | ||
| \\ | \\ | ||
| - | The board view toolbar provided three board level functions and a detailed description may be found in section 3.6.3 of the ACE user guide. The AD9576 primary component link allows the user to navigate to the AD9576 chip view, shown in **Figure 4**, by double clicking this link. The chip view is the primary conduit through which the user can interface with the AD9576. The PPR pin state jumper truth table shows the user the jumper configuration to place a given PPR pin into a PPR state. Used in conjunction with the PPR tables (Table 31 - Table 34) in the [[http:// | + | The board view toolbar provided three board level functions and a detailed description may be found in section 3.6.3 of the ACE user guide. The AD9576 primary component link allows the user to navigate to the AD9576 chip view, shown in **Figure 4**, by double clicking this link. The chip view is the primary conduit through which the user can interface with the AD9576. The PPR pin state jumper truth table shows the user the jumper configuration to place a given PPR pin into a PPR state. Used in conjunction with the PPR tables (Table 31 - Table 34) in the [[adi>static/ |
| ==== Chip View ==== | ==== Chip View ==== | ||
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| ---- | ---- | ||
| ==== Power-on Ready Configuration ==== | ==== Power-on Ready Configuration ==== | ||
| - | This quick start section covers only configuring the AD9576 to execute a PPR load to configure the AD9576 according to Typical Configuration 1 (Asynchronous operation) as outlined in Table 3 of the [[http:// | + | This quick start section covers only configuring the AD9576 to execute a PPR load to configure the AD9576 according to Typical Configuration 1 (Asynchronous operation) as outlined in Table 3 of the [[adi>static/ |
| - Remove any jumpers on P102 and P103 to configure the AD9576 for SPI communication with a PPR load. | - Remove any jumpers on P102 and P103 to configure the AD9576 for SPI communication with a PPR load. | ||
| - Short pin 1 and pin 2 on P402, remove any jumpers from P403, and short pin 2 and pin 3 on P404 to set PPR0 to state 0. | - Short pin 1 and pin 2 on P402, remove any jumpers from P403, and short pin 2 and pin 3 on P404 to set PPR0 to state 0. | ||
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| ==== Session Based Configuration ==== | ==== Session Based Configuration ==== | ||
| - | This quick start section covers only the AD9576 Typical Configuration 2 (Synchronous operation) as outlined in Table 3 of the [[http:// | + | This quick start section covers only the AD9576 Typical Configuration 2 (Synchronous operation) as outlined in Table 3 of the [[adi>static/ |
| - Ensure the Serial Port Configurations Pins, SP0 and SP1, are configured for SPI communication on board power up. | - Ensure the Serial Port Configurations Pins, SP0 and SP1, are configured for SPI communication on board power up. | ||
| - Short pin 1 and pin 2 of P207 and P208 to configure REF0 for a differential input and short pin 2 and pin3 of P211 and P212 to configure REF2 for a XTAL input. | - Short pin 1 and pin 2 of P207 and P208 to configure REF0 for a differential input and short pin 2 and pin3 of P211 and P212 to configure REF2 for a XTAL input. | ||
resources/eval/ad9576-user-guide.txt · Last modified: 19 Apr 2022 17:54 by Petre Minciunescu