The AD9542 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9542 dual digital PLL, synchronizer, and jitter cleaner. The AD9542 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.
The AD9542 can output up to 5 differential (or 10 single-ended) clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs. 10 total outputs and 4 reference inputs are accessible on the evaluation board.
The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9542/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9542 while being powered directly by a step down switching regulator or external LDOs. The AD9542 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9542 Datasheet has been included here. Use this user guide in conjunction with the datasheet that has been provided by ADI.
The following instructions are for setting up the physical connections to the AD9542/PCBZ evaluation board. The user must install the evaluation software prior to connecting the evaluation board for the first time.
The 6V supply powers the following:
By default, the 3.3V ADP2384A switcher output supply supplies a 1.8V Analog Devices ADP7104 Low Noise LDO to power the AD9542. The ADP2384A Switching Regulator can alternately be configured to output 1.8V and directly power the AD9542 to evaluate the AD9542 when powered with a switching power supply.
Refer to the Evaluation Board Software section for details on running the AD9542 evaluation board software.
The AD9542 evaluation board has four reference inputs sources. By default, REF A/AA (Connectors J300 and J301, respectively) have a transformer so that the user can use a signal generator and use REFA in differential mode.
In contrast, REF B/BB (Connectors J302 and J303, respectively) are configured for single-ended CMOS inputs by default. Each reference input logic type is configurable via the evaluation software. * REF B is intended for a DC-coupled, 1.8V/1.2V CMOS input and is terminated with only a 50Ω resistor to ground. * REF BB is intended for a either a DC-coupled, 5V CMOS input, and the on board voltage divider will decrease the input amplitude to 1.8V, or a 3.3V CMOS input which will be reduced to a 1.2V CMOS signal.
By default, the AD9542 system clock input is configured to the on-board 49.152 or 50 MHz crystal. For applications that require either a TCXO or OCXO, The user use can select. Refer to Table 3 for the jumper settings to configure the serial port.
Table 3. System Clock Input Configuration
|SYSCLK Input||Jumper P402||Jumper P403|
|Crystal||Center and Right Pins||Center and Right Pins|
|TCXO||Center and Left Pins||Center and Left Pins|
|OCXO||Center and Top Pins||Center and Bottom Pins|
|J400 SMA Connector||Center and Bottom Pins||Center and Top Pins|
The AD9542 serial port configuration is determined by the logic state of Multi-function pins M4, M5, and M6 upon exit from a reset state. M4 selects which protocol (SPI versus I²C), and M5 and M6 determine the I²C address. Jumper Block P605 allows the user to enable pull-up/down resistors to control the state of Pins M4, M5, and M6 on the AD9542. Refer to Table 4 for the jumper settings to configure the serial port.
Table 4. Serial Port configuration
|Serial Protocol||Slave Address||Jumper P605, Top/Middle/Bottom Row||Jumper P504||Jumper P511|
|SPI||N/A||7-8 / 4-5 / 1-2||SCLK||SDIO|
|I²C||0x48||7-8 / 4-5 / 2-3||SCL||SDA|
|I²C||0x49||7-8 / 5-6 / 2-3||SCL||SDA|
|I²C||0x4A||8-9 / 4-5 / 2-3||SCL||SDA|
|I²C||0x4B||8-9 / 5-6 / 2-3||SCL||SDA|
The AD9542 uses pin strapping of the M3 pin at reset or power-up to enable/disable EEPROM loading. To load the external EEPROM, place a jumper across the center and right pin of the top row of Jumper Block P604. This corresponds to Pins 10 and 11 in Jumper Block P604.
The AD9542 evaluation software allows the user to control the full functionality of the AD9542 through 3-wire SPI communication with the evaluation board. The AD9542 evaluation software is implemented as a component plug-in in ADI’s Analysis | Control | Evaluation (ACE) Software desktop software. ACE allows the evaluation of control of multiple evaluation systems from across ADI’s product portfolio and is designed to educate the user in the functional operation of the component. The ACE wiki page contains system requirement and prerequisite information as well as links to the most recent installer and user guide. The ACE user guide contains detailed information concerning all current aspects of the ACE environment. Much of that information will not be described in this document, but some main ACE operational points relevant to component level functionality will be described. It is highly recommended to review the ACE user guide to discover the myriad capabilities and offerings the ACE environment provides to the user.
Use the following instructions to set up the AD9542 evaluation board software.
Do not connect the evaluation board until the software installation is complete.
(Note that there are a total of four plug-ins that must be installed. Please unzip it first)
Power up and connect the evaluation board to the PC. Open the ACE software. After opening ACE, the user will be presented with the Start View shown in Figure 2. The Explore Local Plug-ins section shows all plug-ins that are locally installed and allows the user to operate the plug-in without the presence of the associated evaluation platform. The Attached Hardware section shows all ADI evaluation platforms which are found to be connected to the PC. The appearance of an Unknown Hardware plug-in means that the plug-in for a detected ADI evaluation platform is not locally installed. Double click on any of the shown plug-ins will open the associated plug-in and navigate to its default view, which is the board view for the AD9542. Note: opening a plug-in from the Explore Local Plug-ins section will not automatically establish a connection with the associated evaluation platform even if the hardware is connected. Only opening a plug-in from the Attached hardware section will automatically establish this connection.
Figure 2. ACE Start Screen
The AD9542 board view can be seen in Figure 3. As the AD9542 evaluation platform is for a single component, the board view has only two main portions, as shown in Figure 3:
The board view toolbar provided three board level functions and a detailed description may be found in section 3.6.3 of the ACE user guide. The AD9542 primary component link allows the user to navigate to the AD9542 chip view, shown in Figure 4, by double clicking this link. The chip view is the primary conduit through which the user can interface with the AD9542.
The chip view is the primary interface used to configure the AD9542. It consists primarily of an interactive block diagram which shows the configuration of the device, calculates the frequency translation, implements frequency based error checking, and allows the user to intuitively configure the AD9542 parameters. It should be noted that in order to synchronize the register content of the software with that of the AD9542, the user must press the ‘Read All’ button in the chip view toolbar in the upper left hand portion of the window.
The configuration wizard simplifies configuring the AD9542 by providing the most commonly needed configuration parameters in a simple user interface. Entered parameters are plugged into a powerful algorithm that calculates the optimal settings ensuring the best possible performance from the AD9542.
The wizard is made up in multiple collapsible1) steps. Each step contains parameters, which are used by the wizard algorithm to calculate an optimized configuration.
Invalid parameters are outlined in red with an error indicator2) in the upper left of the parameter, mouse-over the error indicator for an error description. Example see Figure 5 - OUT0B Expression
Once the desired parameters have been entered and all errors3) have been cleared, the Apply button may be clicked to apply the configuration to the chip.
Figure 5. Configuration Wizard
Some parameters can be entered using expressions.
An expression in it simplest form has three parts, a number followed by the SI prefix and Units. The units are not significant.
|1+0.25 MHz||1.25 MHz|
Supported SI Prefixes
Prefix Value Name Y 10e24 yotta Z 10e21 zetta E 10e18 exa P 10e15 peta T 10e12 tera G 10e9 giga M 10e6 mega k 10e3 kilo m 10e−3 milli u 10e−6 micro n 10e−9 nano p 10e−12 pico f 10e−15 femto a 10e−18 atto z 10e−21 zepto y 10e−24 yocto
A space between the number and SI prefix applies the SI prefix to all numbers in the expression.
|1+0.25 MHz||1250000 Hz|
The following table has some example expressions and evaluated values.
|1+1 Mhz||2 MHz||SI prefix is applied to all numbers.|
|1+1/2 MHz||1.5 MHz|
|(1+1)/2 MHz||1 MHz||Order of operations example.|
|15/2*10 MHz||75 MHz|
|15M/2M*10M Hz||75 MHz|
A detailed explanation of the interaction with the block diagram is explained in the ACE User Guide sections 3.7.1 through 3.7.3. However, it should be noted that the AD9542 chip view heavily leverages the use of configuration menus for blocks with multiple associated bit fields. Clicking on such a block will pop up a menu as pictured in Figure 6.
Clicking and dragging the title bar of the menu will allow the user to relocate the menu at one’s convenience. In order to close the menu, the user may close the ‘close’ button or simply click away from the menu.
The frequency translation of the AD9542 is calculated from reference input frequency to output clock frequency based on the state of the intermediate blocks in between. Not every block in the block diagram impacts the frequency translation, but those that do contain a tool tip displaying the input and output frequencies associated with said block as illustrated in Figure 7.
Changing the configuration of a block that affects the frequency translation will produce an automatic calculation and error checking to inform the user of the impact the change has had on the operation of the AD9543. Any errors resulting from the error checking functionality will display visually as well as the Events Tool View. This view gives the user additional detail regarding the nature of the error and is explained in detail in the ACE User Guide, section 3.9.3.
The AD9542 ACE plug-in as contains a detailed view of the entire register map in either register or bit field based format, known as the Memory Map shown in Figure 8. This view may be accessed by clicking the ‘Proceed to Memory Map’ button in the lower right hand corner of the chip view.
The memory map view is explained in detail in the ACE User Guide section 3.8, but one of the more useful features in the functional group filter shown in the left portion of Figure 8. The AD9542 bit fields have been grouped by relevant functionality and the functional group filter allows the user to quickly and easily switch between viewing only bit fields or registers contained within these macro level functional groups.
The ACE application has the ability to save and recall a given configuration of the software including all currently open plug-ins.
These ‘states’ are referred to as ‘sessions’. The File selection in the application toolbar contains options to create, open, save, or close sessions, as shown in Figure 9.
The left hand section of the Start View also exposes the ability to create and open sessions as well as maintaining a list of recent sessions that may be directly opened.
This quick start section covers the loading of a session file as provided by ADI.