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The AD9525 evaluation board is a compact, easy to use platform for evaluating all features of the AD9525. Two versions of the evaluation board are available : one with a prepopulated external VCO and loop filter (AD9525/PCBZ-VCO) and one with no VCO/VCXO and no loop filter (AD9525/PCBZ). This user guide focuses on the AD9525/PCBZ-VCO, which already has a VCO and loop filter on board. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6. The AD9525 also offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. For more information about the device, see the AD9525 data sheet. This user guide should be used in conjunction with the AD9525 data sheet and the software documentation available at www.analog.com/clocks
The instructions in this section are for setting up the physical connections to the AD9525/PCBZ-VCO evaluation board with a prepopulated VCO. There is another version of the evaluation board (AD9525/PCBZ) that does not contain an external VCO. The two variations of the evaluation boards have slightly different default configurations.
When connecting the evaluation board to a PC for the first time, you must install the evaluation software prior to connecting the evaluation board. If a previous version of the software is already installed, uninstall it before installing the latest version.
Refer to the Evaluation Board Software section for details on running the AD9525 evaluation board software.
To connect signals:
To bypass the PLL:
The AD9525 default register settings configure the device as an eight output clock buffer.
To use an off-board VCO or VCXO:
Note that the right angle SMA connectors on the evaluation board are not optimal for high speed signals. They are provided for ease of use but may cause loss of performance at speeds greater than 1.5 GHz.
The AD9525 PLL requires an external VCO or VCXO and a loop filter containing components tailored for a given application. The third-order passive configuration shown in Figure 2 usually results in the best performance for many applications and is the one found on the evaluation board.
The loop bandwidth of a PLL with a second-order filter (excluding R2 and C3) can be approximated using the following equation:
Because KVCO is determined by the VCO vendor, the bandwidth of the loop can be adjusted by changing the values of ICP and NTOTAL. Note that ICP has a limited range, and NTOTAL is limited by the selectable values of Prescaler P, Divider B, and Divider M. For more information about NTOTAL and ICP, including possible values, see the AD9525 data sheet.
To determine the best loop filter for a given application, use ADIsimCLK™ (Version 1.5 or greater), which is free and can be downloaded from the ADIsimCLK Design and Evaluation Software Web page. This software aids in designing and exploring the capabilities and features of the AD9525, including designing the PLL loop filter.
The AD9525 evaluation board can be purchased with either a Z-Comm CRO2950B-LF external VCO or with no VCO populated. This section discusses a couple of different external VCO possibilities and their respective loop filter designs and performance. Using a high performance VCO with low phase noise allows you to create a low loop bandwidth filter to remove the jitter contained on the input reference clock.
The first setup discussed is the default evaluation board configured with a Z-Comm CRO2950B-LF VCO. With the charge pump set to 1.8 mA and the feedback divider set to 24, the on-board loop filter produces a loop bandwidth of ~6 kHz and ~69° of phase margin. Table 1 shows the parameters used to attain the resulting phase noise measurements described in Figure 4. A phase noise plot of the Z-Comm CRO2950B-LF VCO is shown in Figure 3.
|VCO Operating Frequency||2949.12 MHz|
|Reference Frequency||122.88 MHz|
|Output Frequency||2949.12 MHz|
|Loop Filter Bandwidth||6 kHz|
|Loop Filter Phase Margin||70°|
Table 1. AD9525 Evaluation Board with Z-Comm CRO2950B-LF VCO
Table 2 displays the loop filter component values to achieve ~6 kHz bandwidth and ~69° of phase margin when operating the AD9525 as described in Table 1. Figure 4 shows the output phase noise of the AD9525 using a Z-Comm CRO2950B-LF VCO and the loop filter as defined in Table 2.
|ADIsimCLK||Evaluation Board Location||Component Values (Default)|
Table 2. AD9525 Evaluation Board Default Loop Filter Values for Z-Comm CRO2950B-LF VCO
Figure 5 shows the simulated output phase noise generated by ADIsimCLK using this setup.
The second setup discussed uses the evaluation board with the on-board VCO and loop filter removed. Instead, this setup uses a separate VCO daughter board with a Bowei MVCO1475 VCO and a two-pole loop filter. With the charge pump set to 1.8 mA and the N divider set to 12, the loop filter was designed to give ~11 kHz of bandwidth and ~70° of phase margin. Table 3 shows the parameters used to attain the resulting phase noise measurements described in Figure 7. A phase noise plot of the Bowei MVCO1475 VCO is shown in Figure 6.
|VCO Operating Frequency||1474.56 MHz|
|Reference Frequency||122.88 MHz|
|Output Frequency||1474.56 MHz|
|Loop Filter Bandwidth||11 kHz|
|Loop Filter Phase Margin||73°|
Table 3. AD9525 Evaluation Board with Z-Comm CRO2950B-LF VCO
Table 4 displays the loop filter component values to achieve ~11 kHz bandwidth and ~70° of phase margin when operating the AD9525 as described in Table 1. Figure 7 shows the output phase noise of the AD9525 using a Bowei MVCO1475 and the loop filter as defined in Table 4.
|ADIsimCLK||Component Values (Default)|
Table 4. AD9525 Evaluation Board Loop Filter Values Used with Bowei MVCO1475
Figure 8 shows the simulated output phase noise generated by ADIsimCLK using this setup.
The AD9525 evaluation software allows the user to control the full functionality of the AD9525 through SPI/I2C communication on the evaluation board. Use the following instructions to set up the AD9525 evaluation board software.
Do not connect the evaluation board until the software installation is complete.
Power up and connect the evaluation board to the PC. See the Evaluation Board Hardware section for details on the various connectors on the evaluation board.
AD9525 Evaluation Board in green should be displayed in the bottom left corner of the main window. Alternatively, you can use the software in standalone mode. The standalone mode is useful for verifying register settings for a given PLL setup.See the Evaluation Software Components section for a description of the evaluation software features, and see the Quick Start Guide to the AD9525 PLL section for information about the individual blocks of the AD9525.
The AD9525 quick start guide is intended for direct use with the AD9525/PCBZ-VCO evaluation board containing a prepopulated Z-COMM CRO2950B-LF external VCO. Although the AD9525/PCBZ can be populated with a different external VCO/VCXO, the settings discussed in this quick start guide may not be directly applicable. This guide covers only simple PLL operation to lock the PLL. See the AD9525 data sheet and the Evaluation Software Components section for a detailed explanation of the various AD9525 features.
The AD9525 website contains a setup file to configure the AD9525/PCBZ-VCO to the settings discussed in this section. The setup file can be found online here. After being downloaded, the setup file can be loaded into the evaluation board by opening the AD9525 evaluation software, selecting Load Setup from the File menu, and selecting the appropriate .stp file. The values in Table 5 are used for the example discussed in the Quick Start Steps section.
|Input Frequency||122.88MHz on REFA|
|Output Frequency||2949.12 MHz|
|Phase Detector Frequency||61.44 MHz|
|Feedback Divider (N divider)||48|
|VCO Frequency||2949.12 MHz|
|VCO Divider (M Divider)||1|
|Charge Pump Current (ICP)||8x|
Table 5. Example Values for Quick Start Steps
When the evaluation software is installed, the evaluation board is connected, and the software is loaded, use the following steps to configure and lock the PLL. These steps assume that the input signal is present to REF A, that the evaluation board has not been modified, and that the PLL loop filter is suitable for a given application.