EVALUATING THE AD9467-FMC-250EBZ ANALOG-TO-DIGITAL CONVERTER
This user guide describes the AD9467 evaluation board AD9467-FMC-250EBZ which provides all the support circuitry required to operate the ADC in its various modes and configurations. The application software to interface with the devices is also described.
The AD9467 data sheet provides additional information and should be consulted when using the board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions send an email to firstname.lastname@example.org.
Typical Measurement Setup
Design and Integration Files
Configuring the Board
Before using the software for testing, configure the evaluation board as follows:
Connect one 12V, 2.5A switching power supply (such as the one supplied) to the SDP-H1
board. Connect the Mini-B USB
port of the SDP-H1
board to the PC with the supplied USB
will appear in the Device Manager as shown in Figure 3.
Figure 3. Device Manager Showing SDP-H1
If the Device Manager does not show the SDP-H1
listed as shown in Figure 2, unplug all USB
devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
On the ADC evaluation board, provide a clean, low jitter 250MHz clock source to connector J201 and set the amplitude to 16dBm. This is the ADC Sample Clock.
On the ADC evaluation board, provide a clean, low jitter clock source to connector J100. Use a shielded, RG-58, 50Ohm, coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, pass filter with 50Ohm terminations and appropriate center frequency. (ADI
uses TTE, Allen Avionics, and K
& L band-pass filters)*.
*When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMA or HP8644B signal generators or equivalent*
Visual Analog Setup
On the VisualAnalog “New Canvas” window, click ADC Single AD9467 FFT
Figure 4. Selecting the AD9467 canvas
If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see Figure 5).
Figure 5. Expanding the Display
Click the Settings
button in the ADC Data Capture
block as shown in Figure 6
Figure 6. Changing the ADC Capture Settings
On the General
tab make sure the clock frequency is set to 250MHz
(or other clock frequency).
Figure 7. Setting the clock frequency and capture length
Click on the Capture Board
tab and browse to the ad9467_sdp_h1.bin
file. Click the Program
button. The FPGA_DONE
LED should illuminate on the EVAL-SDP-CH1Z board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site ftp://ftp.analog.com/pub/HSC_ADC_Apps/SDP-H1/ad9467_sdp_h1.bin
Figure 8. Control Window for AD9647
Select the AD9467_16Bit_250MSspiR03.cfg if prompted.
If necessary, click File
Cfg Open AD9467_16Bit_250MSsspiR03.cfg
To enable SPI
communications, click File
Config Controller Dialog
and un-check the SDO Active
Figure 9. Un-Selecting SDO Active in SPIController
Obtaining an FFT
Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 9
Figure 10. AD9467-FMC-250 FFT at 5MHz Analog Input
Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window). Usually about 16dBm of signal power from the signal generator will result in a -1dBFS Fundamental signal.
To save the FFT plot do the following
Click on the Float Form button in the FFT window
Figure 11. Floating the FFT window
Click on File
Save Form As button and save it to a location of choice
FFT plot appears abnormal
If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.
In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (Offset Binary by default).
The FFT plot appears normal, but performance is poor.
Make sure you are using the appropriate band-pass filter on the analog input.
Make sure the signal generators for the clock and the analog input are clean (low phase noise).
If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
Make sure the SPI
config file matches the product being evaluated.
Make sure there isn't any extra stress/torque on the clock and analog input connectors.
The FFT window remains blank after the Run button is clicked
Make sure the evaluation board is securely connected to the SDP-H1
Make sure the FPGA has been programmed by verifying that the FPGA_DONE
LED is illuminated on the EVAL-SDP-CH1Z. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB
and power cord for 15 seconds. Connect again and repeat the SDP-H1
Make sure the correct FPGA bin file was used to program the FPGA.
Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.
Ensure that the ADC has a valid clock input