This QuickStart user guide describes the evaluation boards, AD9266-80EBZ, AD9649-80EBZ, AD9629-80EBZ, and AD9609-80EBZ that are used to evaluate the following Analog Devices, Inc., products: AD9266, AD9649, AD9629, and AD9609. These evaluation boards provide the support circuitry required to operate these devices in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9266 , AD9649, AD9629, and AD9609 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to email@example.com.
Note that, though the 80 MSPS speed grade ADCs and boards are referred to in this document, this user guide is applicable to the other speed grades, as well.
The AD9266/AD9649/AD9629/AD9609 share ADC core characteristics with the AD9269 family of dual ADCs. Additional application information can be found in the Evaluation Board User Guide for Dual ADCs of this family.
Figure 1. Evaluation Board Connection—AD9266-80EBZ/AD9649-80EBZ/AD9629-80EBZ/AD9609-80EBZ (on Left) and HSC-ADC-EVALCZ (on Right)
This section provides quick start procedures for using the AD9266-80EBZ, AD9649-80EBZ, AD9629-80EBZ, or AD9609-80EBZ board.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9266 and AD9649 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate ac performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See Schematics, layout files, bill of materials for schematics and layout diagrams.
This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove E101, E102, E103, E105, E107, E108, and E114 ferrite beads to disconnect the bench supply traces from the on-board LDOs. Note that in some board configurations, some of these ferrite beads might already be uninstalled.
P102 and P103 need to be installed to connect external bench supplies to the board and E109, E110, E111, E112, and E113 need to be populated to connect P102 and P103 to the board power domains. A 1.8 V, 0.5 A supply is needed for P102 Pin 5 (1.8V_DUT_AVDD). The supplies for P103 Pin 1 (DUT_DRVDD) and P103 Pin3 (AUX_DVDD) can be any voltage from 1.8 V to 3.3 V. These two supplies can be shared or separate but if they are separate, the voltages on each must match the other.
Two additional supplies, 3.3V_CLK and 3.3V_AMPVDD, are used to bias the optional input path amplifiers, SPI buffers, and optional AD9517-4 clock chip. If used, each of these supplies need at least a 0.5 A current capability.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG–58, 50 Ω coaxial cable (optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the ADC data sheet). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters directly to the evaluation board.
When an external clock source is used, it must be supplied with a clean signal generator, as previously specified for the analog input signals. Analog Devices evaluation boards typically accept ~2.8 V p-p or 13 dBm sine wave input for the clock. If an external off-board clock source is used, jumper J605 Pin 2 to J605 Pin 3 to disable the oscillator and remove C610 to disconnect the on-board crystal oscillator.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The outputs from the ADC are routed to Connector P902. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.
|J203||In the default state, the MODE_OR pin is an output that indicates an overrange condition. Connecting Pin 1 to Pin 2 connects the MODE_OR pin to an on-board LED to give a visual indication of overrange. SPI writes to Register 0x08 and Register 0x2A can configure the MODE_OR pin to be an input that controls power-down and standby modes. In the case where MODE_OR is configured as an input, connecting Pin 2 to Pin 3 invokes the programmed pin function; see the product datasheet for more information.|
|J302||J302 sets the ADC for SPI communications with the HSC-ADC-EVALCZ.
Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, and Pin 8 to Pin 9 for CSB.
|J605||This jumper enables or disables the on-board crystal oscillator. Jumper Pin 1 to Pin 2 to enable the crystal oscillator; Jumper Pin 2 to Pin 3 to disable the oscillator, in the case where an external off-board clock source is used.|
|J201 and J202||These jumpers select between internal VREF and external VREF.
To choose the internal (on-chip) 1 V reference, connect J201 Pin 2 (DUT_SENSE) to J201 Pin 3 (GND). No jumpers are needed on J202 for the internal (on-chip) 1 V reference.
To use the on-board AD822BRZ 1 V reference, connect J201 Pin 2 (DUT_SENSE) to J201 Pin 1 (1.8V_DUT_AVDD), and connect J202 Pin 2 (DUT_VREF) to J202 Pin 3 (EXT_REF).
To apply a reference voltage from an external off-board source, connect J201 Pin 2 (DUT_SENSE) to J201 Pin 1 (1.8V_DUT_AVDD) and apply the reference voltage to J202 Pin 2 (DUT_VREF). The reference voltage is specified at 1.0 V for the AD9266, AD9649, AD9629, and AD9609.
Figure 2. Default Jumper Connections for AD9266-80EBZ/AD9649-80EBZ/AD9629-80EBZ/AD9609-80EBZ Board
This section explains the default and optional ADC settings or modes allowed on the AD9266-80EBZ and the AD9649-80EBZ boards.
Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet and to P101.
The analog input on the evaluation board is set up for a double balun-coupled analog input with a 50 Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz.
DUT_RBIAS has a default value of 10 kΩ (R203) to ground and is used to set the ADC core bias current. Note that using other than a 10 kΩ, 1% resistor for DUT_RBIAS (R203) may degrade the performance of the device.
The default clock input circuit is derived from a simple transformer coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T601) that adds minimal jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR601 before entering the ADC clock inputs. The AD9266,AD9649,AD9629, and AD9609 ADCs are equipped with an internal 8:1 clock divider to facilitate use with higher frequency clocks. When using the internal divider and a higher input clock frequency, remove CR601 to preserve the slew rate of the clock signal.
The AD9266-80EBZ, AD9649-80EBZ, AD9629-80EBZ, and AD9609-80EBZ boards are set up to be clocked through the transformer coupled input network from the crystal oscillator, Y601. If a different clock source is needed, remove C610 (optional) and place a jumper between Pin 2 and Pin 3 of J605 to disable the oscillator and connect the external clock source to the SMA connector, J602 (labeled ENCODE+).
The AD9266/AD9649/AD9629/AD9609 ADCs can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB pin is tied to AUX_DVDD by removing any jumper on Pin 8 of J302. In this configuration, the SDIO/PDWN pin controls the power-down function, and the SCLK/DFS pin controls the digital output format.
Table 2 and Table 3 specify the settings for pin mode operation. (These settings apply only when CSB is tied high, that is, J302 Pin 8 has no jumper.)
|SDIO/PDWN (J302 Pin 2) Voltage||Device Mode|
|AUX_DVDD (jumper J302 Pin 2 to Pin 3)||Power Down|
|GND (no jumper on J302 Pin 2)||Normal Operation|
|SCLK/DFS (J302 Pin 5) Voltage||Output Format|
|AUX_DVDD (jumper J302 Pin 5 to Pin 6)||Twos Complement|
|GND (no jumper on J302 Pin 5)||Offset Binary|
Note that the settings in Table 2 and Table 3 apply only when CSB is tied high (J302 Pin 8 has no jumper) at power up.
Additional information on the standalone (pin) mode is provided in the AD9266, AD9649, AD9629, and AD9609 data sheets.
To operate the device under test (DUT) using the SPI, follow the jumper settings for J302 as shown in Table 1.
After configuring the board, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 4. VisualAnalog Default Configuration Message
Figure 5. VisualAnalog Window Toolbar, Collapsed Display
Figure 6. VisualAnalog, Main Window Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 7. SPI Controller, CHIP ID(1) Box
Figure 8. SPI Controller, New DUT Button
Figure 9. SPI Controller, CLOCK DIVIDE(B) Box
Figure 10. SPI Controller, Chip Power Mode - Digital Reset Selection
Figure 11. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display
The next step is to adjust the amplitude of the input signal as follows:
Figure 12. Graph Window of VisualAnalog
Lack of SPI communication causes difficulty in configuring the ADC.
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run in VisualAnalog (see Figure 12) is clicked, do the following: