This user guide describes the AD9228, AD9259 and AD9287 evaluation boards, AD9228-65KITZ, AD9259-50KITZ and AD9287-100KITZ, which provide all of the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9228, AD9259 and AD9287 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to email@example.com.
Figure 1. Evaluation Board Connection—AD9228-65KITZ, AD9259-50KITZ or AD9287-100KITZ (on Left) and HSC-ADC-EVALCZ (on Right)
This section provides quick start procedures for using the AD9228-65KITZ, AD9259-50KITZ or AD9287-100KITZ board. Both the default and optional settings are described.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9228, AD9259 and AD9287 in their various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of AD8332. Each input configuration can be selected by changing the connection of various jumpers.
Figure 1 shows the typical bench characterization setup used to evaluate the ac performance of AD9228, AD9259 and AD9287. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.
See the Getting Started section to get started, and visit Design and Integration Files for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board.
When operating the evaluation board in a nondefault condition, L504 to L507 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies.
When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent, as well as 1 m, shielded, RG-58, 50 Ω coaxial cable. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filters with 50 Ω terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K & L Microwave, Inc. The filter should be connected directly to the evaluation board if possible.
The default setup uses the Analog Devices HSC-ADC-FIFO5-INTZ to interface with the Analog Devices standard dual-channel FIOF data capture board (HSC-ADC-EVALCZ). Two of the eight channels can be evaluated at the same time. For more information on the channel settings and optional setting of these boards, visit www.analog.com/hsadcevalboard.
This section explains the default and optional settings or modes allowed on the
AD9228, AD9259 and AD9287 evaluation boards.
Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.
The evaluation board is set up for a transformer-coupled analog input with an optimum 50 Ω impedance match of 190 MHz of bandwidth (see Figure 2). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2.
Figure 2. Evaluation Board Full-Power Bandwidth
VREF is set to 1.0 V by tying the SENSE pin to ground, R237. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 is also included on the evaluation board. Populate R231 and R235 and remove C214. See Voltage Reference section of the datasheet for proper use of the VREF options.
RBIAS has a default setting of 10 kΩ (R201) to ground and is used to set the ADC core bias current.
The default clock input circuit on the evaluation board uses a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and R227 with 0 Ω resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 μF capacitor and remove C210 and C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 datasheet for more information about these and other options.
In addition, an on-board oscillator is available on the OSC201 and can act as the primary clock source. The setup is quick and involves installing R212 with a 0 Ω resistor and setting the enable jumper (J205) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC201) to check the ADC performance.
To enable the power-down feature, short J201 to AVDD on the PDWN pin.
To enable the digital test pattern on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 0000 is enabled. See the SCLK/DTP Pin section of the data sheet for details.
To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J203. If J203 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See SDIO/ODM Pin section of the data sheet for details.
To enable processing of the SPI information on the SDIO and SCLK pins, tie J202 low in the always enable mode. To ignore the SDIO and SCLK information, tie J202 to AVDD.
For users who wish to operate the DUT without using SPI, remove jumpers J202, J203 and J204. This disconnects the CSB, SCLK/DTP and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.
If an alternative data capture method to the setup shown in Figure 1 is used, optional receiver terminations, R206 to R211, can be installed next to high speed backplane connector.
The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive options is in use, some components may need to be populated, in which case all the necessary components are listed in Bill of Materials under Design and Integration Files section. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet.
To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed.
In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary.
After configuring the board, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 4. VisualAnalog Window Toolbar, Collapsed Display
Figure 5. VisualAnalog, Main Window Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 6. SPI Controller, CHIP ID(1) Box
Figure 8. SPI Controller, ADCBase 0 Page
Figure 9. SPI Controller, Example ADC A Page
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 12. Typical FFT, AD9259
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run is clicked, do the following:
If VisualAnalog indicates that the FIFO Capture timed out, do the following: