This user guide describes the AD9484, AD9601, AD9230, AD9211 and AD9626 evaluation boards, AD9484-500EBZ, AD9601-250EBZ, AD9230-250EBZ, AD9211-300EBZ and AD9626-250EBZ which provide all of the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9484, AD9601, AD9230, AD9211 and AD9626 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to firstname.lastname@example.org.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9484, AD9601, AD9230, AD9211 and AD9626 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See the Getting Started section to get started, and Design and Integration Files sections for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at J300. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators (default configuration) that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, JP301 through JP303 can be removed to disconnect the outputs from the on-board LDOs. This enables the user to bias each section of the board individually. Use P300 and P301 to connect a different supply for each section. A 1.8 V supply is needed with 1A current capability for DUT_AVDD and DRVDD; however, it is recommended that separate supplies be used for both analog and digital domains. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. This 3.3 V supply should have a 1 A current capability.
An additional 5V_AVDD is used to bias the optional input path amplifier. If used, this supply should each have 1 A current capability.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or HP 8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude in the signal generators (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ω terminations is recommended. Analog Devices uses band-pass filters from TTE, Allen Avionics and K & L Microwave, Inc. Connect the filters directly to the evaluation board.
If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Analog Devices evaluation boards typically can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The serial LVDS outputs from the ADC are routed to the FPGA on the data capture board. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Connect the switching power supply that is supplied in the evaluation kit between a rated 100V to 240V ac wall outlet (at 47 Hz to 63 Hz) and J300.
The input on the evaluation board is set up for a double balun-coupled analog input with a 50 Ω impedance. The analog input to the AD9484, AD9601, AD9230, AD9211 and AD9626 is a differential buffer. For best dynamic performance, source impedances driving VIN+ and VIN- are matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal.
The analog inputs are self-biased by an on-chip reference to provide a common-mode voltage level of nominally 1.7V.
An internal differential voltage reference creates positive and negative reference voltages that define the 1.5 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of an SPI control.
The AD9484 VREF pin (Pin31) allows the user to monitor the on-board voltage reference or provide an external reference (requires configuration through SPI). The three optional settings are internal Vref (the pin is connected to 20 kΩ to ground), export Vref, and import Vref. See Memory Map section in the data sheet.
The AD9601, AD9230, AD9211 and AD9626 RBIAS pin (Pin31) has a default setting of 10 kΩ (R205) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10 kΩ, 1% resistor for RBIAS may degrade the performance of the device.
The default clock input circuit on the evaluation board uses a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR200 before entering the ADC clock inputs.
The evaluation board is by default set up to be clocked with the transformer-coupled input network connected to the external clock source through the SMA connector, J200 (labeled CLK+).
To enable the power-down feature, add a shorting jumper across P200 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD.
After configuring the board, set up the ADC data capture using the following steps:
Figure 2. VisualAnalog, New Canvas Window
Figure 3. VisualAnalog Window Toolbar, Collapsed Display
Figure 4. VisualAnalog, Main Window Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 5. SPI Controller, CHIP ID(1) Box
Figure 7. SPI Controller, ADCBase 0 Page
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 10. Typical FFT, AD9230
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run is clicked, do the following:
If VisualAnalog indicates that the FIFO Capture timed out, do the following: