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resources:eval:ad9208-3000ebz [18 Aug 2017 20:41] Judy Chuiresources:eval:ad9208-3000ebz [12 Jul 2021 11:42] (current) – added provision for Fsx4 mode for ad9699/ad9208 Mark Arthur Recio
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-======= EVALUATING THE AD9208 ANALOG-TO-DIGITAL CONVERTER =======+======= EVALUATING THE AD9208 / AD9689 / AD9699 ANALOG-TO-DIGITAL CONVERTER ======= 
 ====== Preface ====== ====== Preface ======
-This user guide describes the [[adi>AD9208|AD9208-3000EBZ]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. This guide entails both the hardware and software setup needed to acquire data capture from the evaluation board. This guide assumes the usage of the accompanying [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADS7-V2|ADS7-V2 EBZ High Speed Evaluation Board]]. The user guide for the [[resources/eval/ads7-v2|ADS7-V2]] provides additional information available for consultation during usage. Documents and software tools, where available, can be found at the [[adi>hsadcevalboard|HS-ADC Eval Board homepage]]. For additional information or questions, post a question on [[https://ez.analog.com/community/data_converters |Engineer Zone]], or send an email to **highspeed.converters@analog.com**. <WRAP> </WRAP> <WRAP> </WRAP <WRAP> </WRAP  <WRAP> </WRAP> <WRAP> </WRAP>  +The evaluation board design is shared between the following device variants:[[adi>AD9208|AD9208]] / [[adi>AD9689|AD9689]] / [[adi>AD9699|AD9699]].  
- + 
 +This user guide describes the [[adi>AD9208|AD9208-3000EBZ]], [[adi>AD9689|AD9689-2600EBZ]] and [[adi>AD9689|AD9689-2000EBZ]] evaluation boards which provide all of the support circuitry required to operate the ADC in its various modes and configurations. This guide entails both the hardware and software setup needed to acquire data capture from the evaluation board.  
 + 
 +<WRAP><note>Note: For evaluating [[adi>AD9699|AD9699]], use only [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]] and [[adi>AD9208|AD9208-3000EBZ]] channel A input. </note></WRAP> 
 + 
 +There are two FPGA based data capture boards that can be used to capture data from the [[adi>AD9208|AD9208-3000EBZ]], [[adi>AD9689|AD9689-2600EBZ]] and [[adi>AD9689|AD9689-2000EBZ]] evaluation boards. The available FPGA boards are [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-ADS7-V2|ADS7-V2]] and [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]]. The selection of the FPGA board is based on the maximum line rate required in the evaluation. If the line rate needed in the evaluation is ≤12.5Gbps/lane, the ADS7-V2 can be used for data capture. All applications where the line rate required exceeds 12.5Gbps/lane but is ≤16Gbps/lane will require the ADS8-V1 as the data capture board. The user guides for the [[resources/eval/ads7-v2|ADS7-V2]] and [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]] provide additional information available for consultation during usage. Documents and software tools, where available, can be found at the [[adi>hsadcevalboard|HS-ADC Eval Board homepage]].  
 + 
 +For additional information or questions, post a question on [[ez>community/data_converters |Engineer Zone]], or send an email to **highspeed.converters@analog.com**. The selection table for the FPGA evaluation board is shown below. Only Full BW modes are shown here. However, this table provides a blueprint for FPGA board selection based on the end applications' JESD204B line rate.  
 +^ Evaluation Board Part Number      ^ Sample Rate       ^L.M.F Configuration       ^JESD204B Line Rate (Gbps/lane)     ^Recommended FPGA data capture board      ^ 
 +<fc #0002d3>AD9208-3000EBZ</fc   <fc #0002d3>3.0GSPS</fc    | <fc #0002d3>8.2.1</fc    | <fc #0002d3>15</fc    | <fc #0002d3>ADS8-V1</fc>     | 
 +| <fc #0002d3>AD9208-3000EBZ</fc>    | <fc #0002d3>3.0GSPS</fc>     | <fc #0002d3>8.1.1</fc>     | <fc #0002d3>7.5</fc>     | <fc #0002d3>ADS7-V2 / ADS8-V1</fc>     | 
 +| <fc #0002d3>AD9689-2600EBZ</fc>    | <fc #0002d3>2.6GSPS</fc>     | <fc #0002d3>8.2.1</fc>     | <fc #0002d3>13</fc>     | <fc #0002d3>ADS8-V1</fc>     | 
 +| <fc #0002d3>AD9689-2600EBZ</fc>    | <fc #0002d3>2.5GSPS</fc>     | <fc #0002d3>8.2.1</fc>     | <fc #0002d3>12.5</fc>     | <fc #0002d3>ADS8-V1 / ADS7-V2</fc>     | 
 +| <fc #0002d3>AD9689-2000EBZ</fc>    | <fc #0002d3>2.0GSPS</fc>     | <fc #0002d3>8.2.1</fc>     | <fc #0002d3>10</fc>     | <fc #0002d3>ADS7-V2</fc>     | 
 + 
 +This user guide wiki applies to the following evaluation boards: <WRAP> </WRAP> 
 +^ Evaluation Board Part Number      ^ Description       ^ Board Revision       ^ 
 +| <fc #9400d3>AD9208-3000EBZ</fc>    | <fc #9400d3>Evaluation board for AD9208-3000/AD9699-30000</fc>     | <fc #9400d3>9689CE02C</fc>     | 
 +| <fc #9400d3>AD9689-2600EBZ</fc>    | <fc #9400d3>Evaluation board for AD9689-2600</fc>     | <fc #9400d3>9689CE02C</fc>     | 
 +| <fc #9400d3>AD9689-2000EBZ</fc>    | <fc #9400d3>Evaluation board for AD9689-2000</fc>     | <fc #9400d3>9689CE02C</fc>     | 
 +  
 +Note: The FPGA image in ADS8-V1 does not support lane rates below 2Gbps. Hence, the following modes will not give a valid FFT. All modes listed below use a 3GHz sample clock. 
 +  LMF=411 and LMF=412 for a decimation ratio of 8 
 +  LMF=811 and LMF=812 for a decimation ratio of 4 
 +  LMF=421 and LMF=422 for a decimation ratio of 16 
 +  LMF=821 and LMF=822 for a decimation ratio of 8 
 +  LMF=442 and LMF=444 for a decimation ratio of 30 
 +  LMF=841 and LMF=842 for decimation ratios of 15 and 16
  
-  
 ====== Typical Setup ====== ====== Typical Setup ======
 {{ :resources:eval:user-guides:ad9208:ce02b_fpga_connnections.png?direct&620 |}}<WRAP centeralign> {{ :resources:eval:user-guides:ad9208:ce02b_fpga_connnections.png?direct&620 |}}<WRAP centeralign>
-//Figure 1. [[adi>AD9208|AD9208-3000EBZ]] (Left) and [[resources/eval/ADS7-V2|ADS7-V2]] (Right)//</WRAP>+//Figure 1a. [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]](Left) and [[resources/eval/ADS7-V2|ADS7-V2]] (Right)//</WRAP> 
 +{{ :resources:eval:ADS8-V1EBZ-AD9208 Typ Setup.png?direct&620 |}}<WRAP centeralign> 
 +//Figure 1b. [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]](Left) and [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]] (Right)//</WRAP>
 {{ :resources:eval:user-guides:ad9208:topofboard.png?direct&500 |}}<WRAP centeralign> {{ :resources:eval:user-guides:ad9208:topofboard.png?direct&500 |}}<WRAP centeralign>
-//Figure 2. Top of [[adi>AD9208|AD9208-3000EBZ]] Board//</WRAP>+//Figure 2. Top-side of [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]] Board//</WRAP>
 {{ :resources:eval:user-guides:ad9208:bottomofboard.png?direct&500 |}}<WRAP centeralign> {{ :resources:eval:user-guides:ad9208:bottomofboard.png?direct&500 |}}<WRAP centeralign>
-//Figure 3. Bottom of [[adi>AD9208|AD9208-3000EBZ]] Board//</WRAP>+//Figure 3. Bottom-side of [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]] Board//</WRAP>
  
 <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note> <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note>
  
 ====== Features ====== ====== Features ======
-  * Full featured evaluation board for the [[adi>AD9208|AD9208-3000EBZ]].+  * Full featured evaluation board for the [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]].
   * JESD204B coded serial digital outputs with support for lane rates up to 16Gbps/lane.   * JESD204B coded serial digital outputs with support for lane rates up to 16Gbps/lane.
   * Wide full power bandwidth supports IF sampling of signals up to 9GHz (-3dB point).   * Wide full power bandwidth supports IF sampling of signals up to 9GHz (-3dB point).
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 ====== Helpful Documents ====== ====== Helpful Documents ======
-  * [[adi>AD9208|AD9208]] Data Sheet+  * [[adi>AD9208|AD9208]] / [[adi>AD9689|AD9689]] / [[adi>AD9699|AD9699]] Data Sheet
   * [[ads7-v2|ADS7-V2EBZ]] Data Sheet   * [[ads7-v2|ADS7-V2EBZ]] Data Sheet
   * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual//    * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// 
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   * [[>resources/tools-software/ace>|ACE]] (Analysis | Control | Evaluation)    * [[>resources/tools-software/ace>|ACE]] (Analysis | Control | Evaluation) 
 ====== Design and Integration Files ====== ====== Design and Integration Files ======
-  * {{:resources:eval:ad9208_3000ebz_files.zip|AD9208-3000EBZ Schematic, Gerber layout and BOM}}+  * {{ :resources:eval:ad9208_3000ebz_files.zip |Schematic, Gerber layout and BOM}} 
 +   
 +<WRAP><note>Note: The AD9208-3000EBZ, AD9689-2600EBZ and the AD9689-2000EBZ use the same design files. The only difference is in the ADC choice</note></WRAP>
 ====== Equipment Needed ====== ====== Equipment Needed ======
   * PC running Windows®   * PC running Windows®
   * USB 2.0 port and USB 2.0 High-speed A to B Cable   * USB 2.0 port and USB 2.0 High-speed A to B Cable
-  * [[adi>AD9208|AD9208-3000EBZ]] evaluation board+  * [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] / [[adi>AD9689|AD9689-2000EBZ]] evaluation board
   * [[ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit   * [[ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit
   * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[ads7-v2|ADS7-V2EBZ]])   * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[ads7-v2|ADS7-V2EBZ]])
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 <WRAP centeralign>//Figure 4. [[resources/eval/ADS7-V2|ADS7-V2]] Connector Layout//</WRAP> <WRAP centeralign>//Figure 4. [[resources/eval/ADS7-V2|ADS7-V2]] Connector Layout//</WRAP>
 {{ :resources:eval:user-guides:ad9208:pinlabeling.png?direct&600 |}} {{ :resources:eval:user-guides:ad9208:pinlabeling.png?direct&600 |}}
-<WRAP centeralign>//Figure 5. [[adi>AD9208|AD9208-3000EBZ]] Connector Layout//</WRAP>+<WRAP centeralign>//Figure 5. [[adi>AD9208|AD9208-3000EBZ]] / [[adi>AD9689|AD9689-2600EBZ]] Connector Layout//</WRAP>
 <note tip>Tip: For more information on Sysref and Global Clock (J3, J4, J200, J202), see the [[adi>media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf|JESD204B Survival Guide]].</note> <note tip>Tip: For more information on Sysref and Global Clock (J3, J4, J200, J202), see the [[adi>media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf|JESD204B Survival Guide]].</note>
-<note warning>**Warning: The AD9208-3000EBZ is electrostatic discharge (ESD) sensitive. Handle the device with care, and employ conducting wrist straps or antistatic bags when handling the board.**</note>+<note warning>**Warning: The AD9208-3000EBZ/AD9689-2600EBZ is electrostatic discharge (ESD) sensitive. Handle the device with care, and employ conducting wrist straps or antistatic bags when handling the board.**</note>
  
 ===== Configuring the Board ===== ===== Configuring the Board =====
 {{ :resources:eval:user-guides:ad9208:topofboardjumpers.png?direct&600 |}} {{ :resources:eval:user-guides:ad9208:topofboardjumpers.png?direct&600 |}}
-<WRAP centeralign>//Figure 6. Jumper connections on [[adi>AD9208|AD9208-3000EBZ]]//</WRAP>+<WRAP centeralign>//Figure 6. Jumper connections on [[adi>AD9208|AD9208-3000EBZ]]/[[adi>AD9689|AD9689-2600EBZ]]//</WRAP>
  
 Before using the software for testing, configure the evaluation boards as follows: Before using the software for testing, configure the evaluation boards as follows:
-  - Before connecting the AD9208 to the ADS7-V2, jump the following pins: **P304, P305, P307, P308, P309, P311,** and **P312.** Do not jump **P7** (Temperature Sensor Enable) or **P100** (Power Down / Standby).  Jump **P401** towards the inside of the board, to power the board via FMC. See Figure 6 for all jumper connections.+  - Before connecting the AD9208/AD9689 evaluation board to the ADS7-V2, jump the following pins: **P304, P305, P307, P308, P309, P311,** and **P312.** Do not jump **P7** (Temperature Sensor Enable) or **P100** (Power Down / Standby).  Jump **P401** towards the inside of the board, to power the board via FMC. See Figure 6 for all jumper connections.
   - Ensure that the data capture board is switched to “OFF.” (**S1** on the data capture board) Connect the evaluation board to the data capture board via the FMC connector found on the underside of the board, as shown in Figure 1. Connect the power supply and USB cable to the data capture board.   - Ensure that the data capture board is switched to “OFF.” (**S1** on the data capture board) Connect the evaluation board to the data capture board via the FMC connector found on the underside of the board, as shown in Figure 1. Connect the power supply and USB cable to the data capture board.
   - Turn on the [[ads7-v2|ADS7-V2EBZ]].    - Turn on the [[ads7-v2|ADS7-V2EBZ]]. 
   - The [[ads7-v2|ADS7-V2EBZ]] should appear in the Device Manager as shown in Figure 7.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:0.png?direct&300 |}}</WRAP><WRAP centeralign>//Figure 7. Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - The [[ads7-v2|ADS7-V2EBZ]] should appear in the Device Manager as shown in Figure 7.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:0.png?direct&300 |}}</WRAP><WRAP centeralign>//Figure 7. Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 7, unplug all USB devices from the PC, uninstall and re-install ACE and restart the hardware setup from step 1.   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 7, unplug all USB devices from the PC, uninstall and re-install ACE and restart the hardware setup from step 1.
-  - On the AD9208 evaluation board, provide a clean, low jitter 3 GHz clock source to connector **J201** (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm. This is the ADC Sample Clock. +  - On the AD9208 evaluation board, provide a clean, low jitter clock source to connector **J201** (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm. This is the ADC Sample Clock. Set the sample clock frequency to the rated value of 3GHz for the AD9208 and 2.6GHz for the AD9689
-  - On the ADS7-V2, provide a clean, low jitter clock source to connector **J3** and set the amplitude to 10 dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio </m> </WRAP> <WRAP centeralign><m> Nprime=8 or 16 </m></WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP> <WRAP centeralign> <sub>//(Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes)//</sub> </WRAP> +  - On the ADS7-V2, provide a clean, low jitter clock source to connector **J3** and set the amplitude to 10 dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=(M*Nprime*(10/8)*f_{out}/L)*DataPackingRatio </m>bps/lane, where </WRAP> 
-  - On the AD9208 evaluation board, connect a clean signal generator with low phase noise to **J101** or **J104** via coaxial cable for channels A and B respectively. It is recommended to use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency.+<WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio </m> </WRAP>  
 +<WRAP centeralign><m> Nprime=8 or 16 </m></WRAP> 
 +<WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m> </WRAP>  
 +<WRAP centeralign> <m> DataPackingRatio = 1 (default) or 4/5 (for Fsx4 mode) </m> </WRAP>  
 +<WRAP centeralign> <sub>//(Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes)//</sub> </WRAP> 
 +  - On the AD9208/AD9689 evaluation board, connect a clean signal generator with low phase noise to **J101** or **J104** via coaxial cable for channels A and B respectively. It is recommended to use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency.
  
 ===== ACE Setup ===== ===== ACE Setup =====
   - Download and install [[>resources/tools-software/ace>|ACE]] if it is not already installed.    - Download and install [[>resources/tools-software/ace>|ACE]] if it is not already installed. 
-  - The AD9208 ACE plug-in can be found under the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9208.html#eb-relatedsoftware|9208 Evaluation Board Software Section]] or through ACE's Plug-In Manager (Tools -> Manage Plug-Ins).<WRAP><note tip>Tip: Some browsers (Such as Internet Explorer) may save the file as a .zip file instead of an .acezip file. If this happens, simply download and rename the file with an .acezip file extension.</note></WRAP>+  - The AD9208 / AD9689 ACE plug-in can be found under the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9208.html#eb-relatedsoftware|9208 Evaluation Board Software Section]], [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9689.html#eb-relatedsoftware|9689 Evaluation Board Software Section]] or through ACE's Plug-In Manager (Tools -> Manage Plug-Ins).<WRAP><note tip>Tip: Some browsers (Such as Internet Explorer) may save the file as a .zip file instead of an .acezip file. If this happens, simply download and rename the file with an .acezip file extension.</note></WRAP>
   - Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install.    - Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install. 
   - Click Start -> All Programs -> Analog Devices -> ACE -> ACE   - Click Start -> All Programs -> Analog Devices -> ACE -> ACE
-  - The AD9208 plug-in should appear as in Figure 8 if successfully installed. +  - The AD9208/AD9689 plug-in should appear as in Figure 8 if installed properly<WRAP><note>Note: The AD9699 evaluation board shares the same plugin with AD9208</note></WRAP> 
-  - If the AD9208 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:1.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 8. ACE's AD9208 Plug-in//</WRAP><WRAP><note>Note: Differences may occur between ACE plug-in versions, including the version number seen in Figure 8 above or components in any of the other images below - however, these will not affect the performance of the part nor the fundamental features described in this user guide.</note></WRAP> +  - If the AD9208/AD9689 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:1.png?direct&200 |}}{{ :resources:eval:ace_ad9689-2600_start.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 8. ACE's AD9208 / AD9689 Plug-in//</WRAP><WRAP><note>Note: Differences may occur between ACE plug-in versions, including the version number seen in Figure 8 above or components in any of the other images below - however, these will not affect the performance of the part nor the fundamental features described in this user guide.</note></WRAP> 
-  - Click on the plug-in to open it. This will open the AD9208 Board View. Click the "Program FPGA Image" button to program the ADS7-V2's FPGA for communicating with the AD9208-3000EBZ. Once it is done programming, double click on the blue AD9208 chip (in the middle of the board) to open up the Chip View.<WRAP><note warning>**Warning: Programming the FPGA will power the AD9208 evaluation board via the FMC connector. Removing any of the board's power jumpers (as seen in Figure 6) while the board is on or in operation may cause damage to the board, board components, and/or the chip. Removing the board while it is being powered via the FMC connector may also cause damage to the board.**</note></WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:a1.png?direct&300 |}}</WRAP><WRAP centeralign>//Figure 9. ACE's AD9208 Board View//</WRAP> <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:2.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 10. AD9208 Chip View//</WRAP>+  - Click on the plug-in to open it. This will open the AD9208/AD9689 Board View. Click the "**Program FPGA Image**" button to program the ADS7-V2's FPGA for communicating with the AD9208-3000EBZ/AD9689-2600EBZ. Once it is done programming, double click on the blue AD9208 / AD9689 chip (in the middle of the board) to open up the Chip View.<WRAP><note warning>**Warning: Programming the FPGA will power the AD9208 evaluation board via the FMC connector. Removing any of the board's power jumpers (as seen in Figure 6) while the board is on or in operation may cause damage to the board, board components, and/or the chip. Removing the board while it is being powered via the FMC connector may also cause damage to the board.**</note></WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:a1.png?direct&300 |}}{{ :resources:eval:ace_ad9689-2600_board_view.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 9. ACE's AD9208 / AD9689 Board View// \\ //<fc #ff00ff>Note: The plugin might display some warnings/errors. These can be ignored for now</fc>//</WRAP> <WRAP>{{ :resources:eval:fig_10.jpg?direct&600 |}}</WRAP><WRAP centeralign>//Figure 10. AD9208 Chip View// \\ //<fc #ff00ff>The AD9689 Chip view is similar to the AD9208 chip view</fc>//</WRAP> 
 ==== Obtaining a Full Bandwidth Capture ==== ==== Obtaining a Full Bandwidth Capture ====
-  - Under Initial Configuration, change the number of Virtual Converters to 1. Click Apply to apply the chip settings. Set the reference clock to 375 MHz to match these settings.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:3.png?direct&400 |}}</WRAP><WRAP centeralign>//Figure 11. Chip Settings//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:4.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 12. Apply Settings//</WRAP>+  - Under Initial Configuration, change the number of Virtual Converters to 1. Click Apply to apply the chip settings. Set the reference clock to the appropriate frequency as recommended by the ACE plugin.<WRAP>{{ :resources:eval:fig_12.jpg?direct&400 |}}{{ :resources:eval:ace_ad9689-2600_summary.png?direct&400 |}}</WRAP><WRAP centeralign>//Figure 11. Chip Settings, AD9208-3000 on top, AD9689-2600 on bottom//</WRAP><WRAP>{{ :resources:eval:figure_12.jpg?direct&400 |}}</WRAP><WRAP centeralign>//Figure 12. Apply Settings//</WRAP>
   - The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the Read All button.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:5.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 13. Read All//</WRAP>   - The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the Read All button.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:5.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 13. Read All//</WRAP>
   - Issue a data path reset to the AD9208 by clicking its checkbox and clicking Apply Changes. The data path reset bit will automatically self clear.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:6.png?direct&250 |}}</WRAP><WRAP centeralign>//Figure 14. Data path reset//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:7.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 15. Apply Changes//</WRAP>   - Issue a data path reset to the AD9208 by clicking its checkbox and clicking Apply Changes. The data path reset bit will automatically self clear.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:6.png?direct&250 |}}</WRAP><WRAP centeralign>//Figure 14. Data path reset//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:7.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 15. Apply Changes//</WRAP>
   -  If the PLL Lock Lost indicator lights up, you can reset it by powering down the JESD link using the Link Control dropdown box, and clicking Apply Changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:8.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 16. PLL Lock Lost//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:9.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 17. Link Power Down//</WRAP>   -  If the PLL Lock Lost indicator lights up, you can reset it by powering down the JESD link using the Link Control dropdown box, and clicking Apply Changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:8.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 16. PLL Lock Lost//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:9.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 17. Link Power Down//</WRAP>
   - Enable the link again and Apply Changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:11.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 18. Link Enable//</WRAP>   - Enable the link again and Apply Changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:11.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 18. Link Enable//</WRAP>
-  - Click Proceed to Analysis. This is ACE's Analysis tool for data from the ADC, displaying both sample plots and FFTs. Click on DDCFFT and run one capture.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:12.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 19. Analysis Tool//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:13.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 20. Display FFTs//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:14.png?direct&150 |}}</WRAP><WRAP centeralign>//Figure 21. Run one capture//</WRAP><WRAP><note important>Tip: Capturing data using another program (e.g. VisualAnalog, proprietary code, etc.) while using ACE concurrently may cause errors in ACE's data capture. If this occurs, the best solution is to restart the evaluation boards and work solely via ACE, or to setup the part in ACE then capture solely in the other program.</note></WRAP>+  - Click Proceed to Analysis. This is ACE's Analysis tool for data from the ADC, displaying both sample plots and FFTs. Click on FFT and run one capture.<WRAP>{{ :resources:eval:screen_shot_01-04-18_at_04.37_pm.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 19. Analysis Tool//</WRAP><WRAP>{{ :resources:eval:screen_shot_01-04-18_at_04.36_pm.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 20. Display FFTs//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:14.png?direct&150 |}}</WRAP><WRAP centeralign>//Figure 21. Run one capture//</WRAP><WRAP><note important>Tip: Capturing data using another program (e.g. VisualAnalog, proprietary code, etc.) while using ACE concurrently may cause errors in ACE's data capture. If this occurs, the best solution is to restart the evaluation boards and work solely via ACE, or to setup the part in ACE then capture solely in the other program.</note></WRAP>
   - A successful capture is shown below, with a filtered 255 MHz signal input to Channel A. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:15.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 22. AD9208-3000 FFT at 255MHz Analog Input to Channel A//</WRAP>   - A successful capture is shown below, with a filtered 255 MHz signal input to Channel A. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:15.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 22. AD9208-3000 FFT at 255MHz Analog Input to Channel A//</WRAP>
-  - In order to get a capture from Channel B, use the Register Debugger within ACE and write 0x01 to register 0x0564. Click the Read All button. Repeat Step 6. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:15p0.png?direct&200 |}}{{ :resources:eval:user-guides:ad9208:stepbystep:5.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 23. ACE Register Debugger//</WRAP>+  - In order to get a capture from Channel B, use the Register Debugger within ACE and write 0x01 to register 0x0564. Click the **Read All** button. Repeat Step 6. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:15p0.png?direct&200 |}}{{ :resources:eval:user-guides:ad9208:stepbystep:5.png?direct&100 |}}</WRAP><WRAP centeralign>//Figure 23. ACE Register Debugger//</WRAP> 
 + 
 ==== Obtaining a DDC Capture ==== ==== Obtaining a DDC Capture ====
 +The procedure to obtain a FFT using DDC is the same between AD9208 and AD9689. The steps below use the AD9208 as the example, but the same can be done to the AD9689 plugin with the sample rate set to 2.6GSPS.
   - This section explains the steps needed to setup the AD9208-3000EBZ in a DDC (Decimal Down Converter) setup as shown in Figure 24. <WRAP>{{ :resources:eval:lmfs_4421_generic.png?direct |}}</WRAP><WRAP centeralign>//Figure 24. AD9208 DDC setup block diagram//</WRAP>   - This section explains the steps needed to setup the AD9208-3000EBZ in a DDC (Decimal Down Converter) setup as shown in Figure 24. <WRAP>{{ :resources:eval:lmfs_4421_generic.png?direct |}}</WRAP><WRAP centeralign>//Figure 24. AD9208 DDC setup block diagram//</WRAP>
-  - Under Initial Configuration, set the Chip Operating Mode for two DDCs. The DDC settings will become available, and automatically set up for Decimate-by-4 mode. For the decimation, select "HB1_HB2_HB3 Complex" - three half-band filters, i.e. Decimate-by-8. Set the number of lanes to 4, the number of converters to 4, and the number of Octets per Frame to 2. Apply the settings. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:16.png?direct&400 |}}</WRAP><WRAP centeralign>//Figure 25. DDC Chip Settings//</WRAP>+  - Under Initial Configuration, set the Chip Operating Mode for two DDCs. **For AD9699, set the DDC inputs to Channel A only.** The DDC settings will become available, and automatically set up for Decimate-by-4 mode. For the decimation, select "HB1_HB2_HB3 Complex" - three half-band filters, i.e. Decimate-by-8. Set the number of lanes to 4, the number of converters to 4, and the number of Octets per Frame to 2. Apply the settings. <WRAP>{{ :resources:eval:fig_25.jpg?direct&600 |}}</WRAP><WRAP centeralign>//Figure 25. DDC Chip Settings//</WRAP>
   - The chip view will update to reflect the changes. Click on the NCO block to change the Numerically Controlled Oscillator's frequency to 1300 MHz. Enable the 6dB gain for the DDC from the dropdown menu. Click Apply Changes to apply both.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:17.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 26. NCO Frequency Setting//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:18.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 27. DDC Gain//</WRAP>   - The chip view will update to reflect the changes. Click on the NCO block to change the Numerically Controlled Oscillator's frequency to 1300 MHz. Enable the 6dB gain for the DDC from the dropdown menu. Click Apply Changes to apply both.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:17.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 26. NCO Frequency Setting//</WRAP><WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:18.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 27. DDC Gain//</WRAP>
   - Navigate to the second DDC (DDC1) and make the same changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:19.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 28. DDC Selection//</WRAP>   - Navigate to the second DDC (DDC1) and make the same changes.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:19.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 28. DDC Selection//</WRAP>
   - In Analysis, run a capture. DDC0 can be selected from Channel A and DDC1 can be selected from Channel B.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:23.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 29. DDC Selection//</WRAP>   - In Analysis, run a capture. DDC0 can be selected from Channel A and DDC1 can be selected from Channel B.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:23.png?direct&200 |}}</WRAP><WRAP centeralign>//Figure 29. DDC Selection//</WRAP>
   - A successful capture is shown below, with a filtered 1305 MHz signal input to Channel A / DDC0.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:22.png?direct&600 |}}</WRAP><WRAP centeralign>//Figure 30. AD9208-3000 DDC FFT at 1305MHz Analog Input to Channel A; NCO tuning frequency = 1300MHz//</WRAP>    - A successful capture is shown below, with a filtered 1305 MHz signal input to Channel A / DDC0.<WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:22.png?direct&600 |}}</WRAP><WRAP centeralign>//Figure 30. AD9208-3000 DDC FFT at 1305MHz Analog Input to Channel A; NCO tuning frequency = 1300MHz//</WRAP> 
 +
 +==== Setting up AD9208/AD9699 Fsx4 Mode ====
 +Fsx4 mode on AD9208/AD9699 is only supported using [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]]. The procedure below shows how to use Fsx4 mode with ADC sampling frequency of 3GHz and a Reference clock of 600MHz.
 +  - On the Chip Application Mode tab, click on the Fsx4 Operation dropdown menu and select "L/M = 4/1" for AD9699, "L/M = 8/2" for AD9208. <WRAP>{{ :resources:eval:fsx4_mode.jpg?direct&600 |}}</WRAP><WRAP centeralign>//Figure 31. AD9699 Fsx4 mode setting//</WRAP> 
 +  - Source the required REFCLK to the [[adi>en/content/CU_High-Speed_ADC_FIFO_evaluation_tools/fca.html#ADS8-V1|ADS8-V1]].
 +  - Click Proceed to Analysis. This is ACE's Analysis tool for data from the ADC, displaying both sample plots and FFTs. Click on FFT and run one capture.
 +  -  A successful capture is shown below, with a filtered 255 MHz signal input to Channel A. <WRAP>{{ :resources:eval:user-guides:ad9208:stepbystep:15.png?direct&500 |}}</WRAP><WRAP centeralign>//Figure 32. AD9208-3000 Fsx4 FFT at 255MHz Analog Input to Channel A//</WRAP>
  
 ====== Troubleshooting Tips ====== ====== Troubleshooting Tips ======
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   * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts.   * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts.
   * Check Test Point 307 - test point for the SPI_VDD supply domain, jumper P312 - and make sure it is around 1.9 volts.    * Check Test Point 307 - test point for the SPI_VDD supply domain, jumper P312 - and make sure it is around 1.9 volts. 
-  * To test SPI operation, attempt to both read and write to register 0x000A using ACE's Register Debugger (see Figure 23). This register is an open register available for testing memory reads and writes. If the value written to this register does not reset after writing it, SPI is operational. +  * To test SPI operation, attempt to both read and write to register 0x000A using ACE's Register Debugger (see Figure 23). This register is an open register available for testing memory reads and writes. If the register reads back the same value written to it, SPI is operational. 
   * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.   * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.
   * Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed.    * Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed. 
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 === EVALUATION BOARD FAILS TO CAPTURE DATA === === EVALUATION BOARD FAILS TO CAPTURE DATA ===
   * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.   * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.
-  * Check the Clock Detect register 0x011B to see if the inputted clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator inputting on connector J201. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. +  * Check the Clock Detect register 0x011B to see if the sample clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator input on connector J201. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. 
-  * Check the PLL Locked indicator (see Figure 16) or register 0x056F (PLL Status). If the light is green / if the register reads back 0x80, the PLL is locked. If it is not locked: +  * Check the PLL Locked indicator (see Figure 16) or register 0x056F (PLL Status). If the light in the plugin chip view is green / if the register reads back 0x80, the PLL is locked. If it is not locked: 
-    * Check the clock being inputted to connector J201 (in this guide, 3 GHz). +    * Check the clock being input to connector J201 (in this guide, 3 GHz or 2.6GHz depending on the part). 
-    * Check the JESD settings under the Initial Configuration. Reference the AD9208 datasheet for supported lane options.+    * Check the JESD204B settings under the Initial Configuration. Reference the [[adi>AD9208|AD9208]] / [[adi>AD9689|AD9689]] / [[adi>AD9699|AD9699]] datasheet for supported lane options.
     * Check the reference clock and make sure it matches your JESD settings.      * Check the reference clock and make sure it matches your JESD settings. 
-    * Make sure P100 (Power Down / Standby Jumper, see Figure 6) is not jumped. +    * Make sure P100 (Power Down / Standby Jumper, see Figure 6) is not jumped. 
  
resources/eval/ad9208-3000ebz.1503081680.txt.gz · Last modified: 18 Aug 2017 20:41 by Judy Chui