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resources:eval:ad9094-1000ebz [10 Aug 2022 04:41] – [Helpful Documents] John Xavier Toledo | resources:eval:ad9094-1000ebz [23 Sep 2022 09:48] (current) – James Peevee Salenga | ||
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- | ====== EVALUATING THE AD9094 | + | ====== EVALUATING THE AD9094 |
===== Preface ===== | ===== Preface ===== | ||
- | This user guide describes the AD9094 evaluation board AD9094-1000EBZ which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. | + | This user guide describes the [[adi>AD9094|AD9094]] |
^ Evaluation Board Part Number | ^ Evaluation Board Part Number | ||
| <fc # | | <fc # | ||
- | \\ | + | The [[adi> |
+ | \\ | ||
+ | \\ | ||
+ | For additional information or questions, post a question on [[ez> | ||
+ | \\ | ||
\\ | \\ | ||
- | The AD9094 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at [[adi> | ||
===== AD9094 Evaluation Board ===== | ===== AD9094 Evaluation Board ===== | ||
- | {{ : | + | {{ : |
// | // | ||
===== Typical Measurement Setup ===== | ===== Typical Measurement Setup ===== | ||
The [[adi> | The [[adi> | ||
- | {{ : | + | |
- | // | + | {{ : |
+ | // | ||
+ | |||
+ | {{: | ||
+ | // | ||
</ | </ | ||
+ | |||
+ | <note tip>Tip: For more information on Sysref (J200), see the [[adi> | ||
+ | |||
+ | <note warning> | ||
===== Features ===== | ===== Features ===== | ||
* Full featured evaluation board for the [[adi> | * Full featured evaluation board for the [[adi> | ||
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* VisualAnalog® and SPI controller software interfaces | * VisualAnalog® and SPI controller software interfaces | ||
===== Helpful Documents ===== | ===== Helpful Documents ===== | ||
- | * [[adi>AD9094|AD9094]] | + | * [[adi>media/ |
* [[http:// | * [[http:// | ||
- | * [[adi> | + | * [[adi>media/ |
* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
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- Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in the figure for the **Evaluation Board Connection**. | - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in the figure for the **Evaluation Board Connection**. | ||
- Make sure the jumpers are placed on the evaluation board as highlighted in green in the figure **AD9094 Evaluation Board**. | - Make sure the jumpers are placed on the evaluation board as highlighted in green in the figure **AD9094 Evaluation Board**. | ||
- | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. | + | - Ensure that the S1 on ADS7-V2 is off. Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. |
- Turn on the [[ads7-v2|ADS7-V2EBZ]]. | - Turn on the [[ads7-v2|ADS7-V2EBZ]]. | ||
- The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | ||
- If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | ||
- | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector | + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector |
- On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | ||
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
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- Click Start < | - Click Start < | ||
- On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9094 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode. If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ : | - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9094 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode. If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ : | ||
- | - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ : | + | - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V2 board indicating that the FPGA has been correctly programmed. {{ : |
+ | <note warning> | ||
- Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set at the sample rate. For example, if the input clock to the AD9094 is 1000 MHz then set the **Clock Frequency (MHz)** to 1000 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). | - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set at the sample rate. For example, if the input clock to the AD9094 is 1000 MHz then set the **Clock Frequency (MHz)** to 1000 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). | ||
{{ : | {{ : | ||
- | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ : | + | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon {{ : |
- On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked. | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked. | ||
- Click **OK** | - Click **OK** | ||
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- The default Chip Application Mode for the [[adi> | - The default Chip Application Mode for the [[adi> | ||
- In order to change the settings for each channel, double-click on the AD9094 icon from the **AD9094 Eval Board** view (highlighted in the figure below). {{ : | - In order to change the settings for each channel, double-click on the AD9094 icon from the **AD9094 Eval Board** view (highlighted in the figure below). {{ : | ||
- | - This will bring up the AD9094 device view showing more specific settings for each pair and channel. The device view shows one pair of the AD9094 at a time. The **ADC Pair Selection** drop down box is used to select the current pair. To select the desired pair (Pair AB or Pair CD) select the desired pair from the drop down box. This sets the current changes to affect the select pair only. The settings can now be configured for each channel. | + | - This will bring up the AD9094 device view showing more specific settings for each pair and channel. The device view shows one pair of the AD9094 at a time. The **ADC Pair Selection** drop down box is used to select the current pair. To select the desired pair (Pair AB or Pair CD) select the desired pair from the drop down box. This sets the current changes to affect the select pair only. The settings can now be configured for each channel. |
- The device view in ACE also has controls for the analog input controls. | - The device view in ACE also has controls for the analog input controls. | ||
- The **Memory Map View** can be accessed from the AD9094 **Device View**. | - The **Memory Map View** can be accessed from the AD9094 **Device View**. | ||
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- Click on File < | - Click on File < | ||
+ | ====== Troubleshooting Tips ====== | ||
+ | === EVALUATION BOARD ISN'T FUNCTIONING PROPERLY === | ||
+ | * It is possible that a board component has been rendered inoperable by ESD, removing a jumper during powered operation, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows: | ||
+ | |||
+ | ^ Domain | ||
+ | | AVDD_0P9 | ||
+ | | AVDD_1P8 | ||
+ | | AVDD_BUF | ||
+ | | DRVDD_0P9 | ||
+ | | AVDD_1P8_PLL | ||
+ | | DVDD_0P9 | ||
+ | | AVDD_1P8_SPI | ||
+ | |||
+ | * If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F401 (next to P401), a component may have been damaged. This may have occurred from jumper or board removal while being actively powered (See the warning in the [[resources/ | ||
+ | |||
+ | === EVALUATION BOARD IS NOT COMMUNICATING WITH THE ADS7-V2 / NO SPI COMMUNICATION === | ||
+ | * Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (FPGA_DONE) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed. | ||
+ | * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_0P9. On the ADS7-V2, the common mode voltage should be around 1.2 volts. | ||
+ | * Check Test Point 307 - test point for the AVDD_1P8_SPI supply domain, jumper P312 - and make sure it is around 1.8 volts. | ||
+ | * To test SPI operation, attempt to both read and write to register 0x000A using ACE's Register Debugger (View → Register Debugger). This register is an open register available for testing memory reads and writes. If the value written to this register does not reset after writing it, SPI is operational. | ||
+ | * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication. | ||
+ | * Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed. | ||
+ | === EVALUATION BOARD FAILS TO CAPTURE DATA === | ||
+ | * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips. | ||
+ | * Check the Clock Detect register 0x011B to see if the inputted clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator inputting on connector J203. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. | ||
+ | * Check the PLL Locked indicator or register 0x056F (PLL Status). If the light is green / if the register reads back 0x80, the PLL is locked. If it is not locked: | ||
+ | * Check the clock being inputted to connector J203 | ||
+ | * Check the JESD settings under the Initial Configuration. Reference the [[adi> | ||
+ | * Check the reference clock and make sure it matches your JESD settings. | ||
+ | * Make sure P100 (Power Down / Standby Jumper) is not jumped. |