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resources:eval:ad9094-1000ebz [10 Aug 2022 04:41] – [Helpful Documents] John Xavier Toledoresources:eval:ad9094-1000ebz [23 Sep 2022 09:48] (current) – James Peevee Salenga
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-====== EVALUATING THE AD9094 QUAD CHANNEL 1 GSPS ADC ======+====== EVALUATING THE AD9094 ANALOG-TO-DIGITAL CONVERTER ======
 ===== Preface ===== ===== Preface =====
-This user guide describes the AD9094 evaluation board AD9094-1000EBZ which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described.  The user guide wiki applies to the follow evaluation boards:+This user guide describes the [[adi>AD9094|AD9094]] evaluation board [[adi>AD9094|AD9094-1000EBZ]] which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described.  The user guide wiki applies to the following evaluation boards:
 ^ Evaluation Board Part Number      ^ Description       ^Board Revision       ^ ^ Evaluation Board Part Number      ^ Description       ^Board Revision       ^
 | <fc #9400d3>AD9094-1000EBZ</fc>    | <fc #9400d3>Evaluation board for AD9094-1000</fc>     | <fc #9400d3>9694CE04A</fc>     | | <fc #9400d3>AD9094-1000EBZ</fc>    | <fc #9400d3>Evaluation board for AD9094-1000</fc>     | <fc #9400d3>9694CE04A</fc>     |
-\\ +The [[adi>media/en/technical-documentation/data-sheets/ad9094.pdf|AD9094 data sheet]] provides additional information and should be consulted when using the evaluation board. This guide assumes the usage of the accompanying [[ads7-v2|ADS7-V2EBZ]] High Speed Evaluation Board. The user guide for the [[http://wiki.analog.com/resources/eval/ads7-v2 | ADS7-V2]] provides additional information available for consultation during usage. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. 
 +\\ 
 +\\ 
 +For additional information or questions, post a question on [[ez>community/data_converters |Engineer Zone]], or send an email to **highspeed.converters@analog.com**. 
 +\\
 \\ \\
-The AD9094 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at  [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. 
 ===== AD9094 Evaluation Board ===== ===== AD9094 Evaluation Board =====
-{{ :resources:eval:ad9694_jumpers_new_board.jpg?direct800 |}}<WRAP centeralign>+{{ :resources:eval:ad90941000ebztop.png |}}<WRAP centeralign>
 //[[adi>AD9094|AD9094]] Evaluation Board //</WRAP> //[[adi>AD9094|AD9094]] Evaluation Board //</WRAP>
 ===== Typical Measurement Setup ===== ===== Typical Measurement Setup =====
 The [[adi>AD9094|AD9094-1000EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figures below show the [[adi>AD9094|AD9094-1000EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]]. The [[adi>AD9094|AD9094-1000EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figures below show the [[adi>AD9094|AD9094-1000EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]].
-{{ :resources:eval:ad9694_connection_new_board.jpg?direct&800 |}}<WRAP centeralign> + 
-//Evaluation Board Connection—[[adi>AD9094|AD9094-1000EBZ]]//+{{ :resources:eval:ad9694_jumpers_new_board.jpg?direct800 |}}<WRAP centeralign> 
 +//[[adi>AD9094|AD9094-1000EBZ]] Jumpers Placement //</WRAP> 
 + 
 +{{:resources:eval:ad9694_connection_new_board_v1.png?1000|}}<WRAP centeralign> 
 +//Evaluation Board Connection—[[adi>AD9094|AD9094-1000EBZ]](Left) and [[resources/eval/ADS7-V2|ADS7-V2]] (Right)//
 </WRAP> </WRAP>
 +
 +<note tip>Tip: For more information on Sysref (J200), see the [[adi>media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf|JESD204B Survival Guide]].</note>
 +
 +<note warning>**Warning: The AD9094-1000EBZ is electrostatic discharge (ESD) sensitive. Handle the device with care, and employ conducting wrist straps or antistatic bags when handling the board.**</note>
 ===== Features ===== ===== Features =====
   * Full featured evaluation board for the [[adi>AD9094|AD9094]]   * Full featured evaluation board for the [[adi>AD9094|AD9094]]
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   * VisualAnalog® and SPI controller software interfaces   * VisualAnalog® and SPI controller software interfaces
 ===== Helpful Documents ===== ===== Helpful Documents =====
-  * [[adi>AD9094|AD9094]] Data Sheet+  * [[adi>media/en/technical-documentation/data-sheets/ad9094.pdf|AD9094 Data Sheet]]
   * [[http://wiki.analog.com/resources/eval/ads7-v2 | ADS7-V2]] User Guide   * [[http://wiki.analog.com/resources/eval/ads7-v2 | ADS7-V2]] User Guide
-  * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// +  * [[adi>media/en/technical-documentation/app-notes/an-905.pdf|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// 
   * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//   * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//
   * [[adi>an-877|AN-877 Application Note]], //Interfacing to High-Speed ADCs using SPI//   * [[adi>an-877|AN-877 Application Note]], //Interfacing to High-Speed ADCs using SPI//
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   - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in the figure for the **Evaluation Board Connection**.   - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in the figure for the **Evaluation Board Connection**.
   - Make sure the jumpers are placed on the evaluation board as highlighted in green in the figure **AD9094 Evaluation Board**.   - Make sure the jumpers are placed on the evaluation board as highlighted in green in the figure **AD9094 Evaluation Board**.
-  - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. +  - Ensure that the S1 on ADS7-V2 is off. Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. 
   - Turn on the [[ads7-v2|ADS7-V2EBZ]].    - Turn on the [[ads7-v2|ADS7-V2EBZ]]. 
   - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>   - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP>
   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.   - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
-  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J204 and set the amplitude to 14dBm. This is the ADC Sample Clock.+  - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock.
   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>   - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP>
   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9094 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.   - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD9094 make sure the clock source has a 50% duty cycle.  For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source.
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   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog   - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog
   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9094 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9094_highlight.png?nolink |}}<WRAP centeralign>//Select the [[adi>AD9094|AD9094]] canvas //</WRAP>   - On the VisualAnalog “New Canvas” window, and select the desired canvas. **Note: The current canvases for VisualAnalog only support operating both pairs of channels in the AD9094 in the same chip operating mode with the same decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also be in full bandwidth mode.  If Pair AB is in real DDC0/DDC1 mode with a decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a decimation rate of 2.**{{ :resources:eval:newcanvas9094_highlight.png?nolink |}}<WRAP centeralign>//Select the [[adi>AD9094|AD9094]] canvas //</WRAP>
-  - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP>+  - Next, program the FPGA in VisualAnalog by clicking into the **ADC Data Capture Settings** block and selecting the **Capture Board** tab. Use the **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V2 board indicating that the FPGA has been correctly programmed. {{ :resources:eval:9694_program_FPGA.png?nolink |}}<WRAP centeralign>//Programming the [[ads7-v2|ADS7-V2EBZ]]//</WRAP> 
 +<note warning>**Warning: Programming the FPGA will power the AD9094 evaluation board via the FMC connector. Removing any of the board's power jumpers while the board is on or in operation may cause damage to the board and/or chip. Removing the board while it is being powered via the FMC connector may also cause damage to the board.**</note>
   - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set at the sample rate. For example, if the input clock to the AD9094 is 1000 MHz then set the **Clock Frequency (MHz)** to 1000 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).   - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set at the sample rate. For example, if the input clock to the AD9094 is 1000 MHz then set the **Clock Frequency (MHz)** to 1000 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel).
 {{ :resources:eval:9094data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP> {{ :resources:eval:9094data_capture_settings_general.png |}}<WRAP centeralign>//Changing the ADC Capture Settings//</WRAP>
-  - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>+  - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon {{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP>
   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked.   - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked.
   - Click **OK**   - Click **OK**
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     - The default Chip Application Mode for the [[adi>AD9094|AD9094-1000EBZ]] is Full BW mode.  In this example the clock frequency will be set to **1000 MHz**, the clock divider set to **Divide by 1**, and the chip operating mode set to **Full BW Mode**. Once the settings have been entered, click **Apply**.  This will configure the device with the selected settings and provide an **Initial Configuration Summary** which will summarize the settings that have been loaded into the AD9094 and also provide the frequency for the required FPGA reference clock. {{ :resources:eval:9094_ace_initial_config.png?link |}}<WRAP centeralign>//Default Application Mode - Full BW Mode (click to enlarge)//</WRAP>     - The default Chip Application Mode for the [[adi>AD9094|AD9094-1000EBZ]] is Full BW mode.  In this example the clock frequency will be set to **1000 MHz**, the clock divider set to **Divide by 1**, and the chip operating mode set to **Full BW Mode**. Once the settings have been entered, click **Apply**.  This will configure the device with the selected settings and provide an **Initial Configuration Summary** which will summarize the settings that have been loaded into the AD9094 and also provide the frequency for the required FPGA reference clock. {{ :resources:eval:9094_ace_initial_config.png?link |}}<WRAP centeralign>//Default Application Mode - Full BW Mode (click to enlarge)//</WRAP>
     - In order to change the settings for each channel, double-click on the AD9094 icon from the **AD9094 Eval Board** view (highlighted in the figure below). {{ :resources:eval:9094_ace_initial_config_highlight.png?nolink |}}<WRAP centeralign>//Double-click the AD9094 Icon in the Eval Board View//</WRAP>     - In order to change the settings for each channel, double-click on the AD9094 icon from the **AD9094 Eval Board** view (highlighted in the figure below). {{ :resources:eval:9094_ace_initial_config_highlight.png?nolink |}}<WRAP centeralign>//Double-click the AD9094 Icon in the Eval Board View//</WRAP>
-    - This will bring up the AD9094 device view showing more specific settings for each pair and channel. The device view shows one pair of the AD9094 at a time.  The **ADC Pair Selection** drop down box is used to select the current pair.  To select the desired pair (Pair AB or Pair CD) select the desired pair from the drop down box.  This sets the current changes to affect the select pair only.  The settings can now be configured for each channel.  Once the settings are configured click **Apply Changes** in the upper left of the device view.  This will load the setting changes to the selected ADC pair and channel(s). If the settings are desired for all four channels then click the **Apply** button in the **AD9094 Configuration** window on the left of the screen.  This loads the current settings to all channels in the device.{{ :resources:eval:9094_ace_device_view_read_all.png?link |}}<WRAP centeralign>//Figure 15. Pair AB - Channel A and Channel B NSR Settings (click to enlarge)//</WRAP>+    - This will bring up the AD9094 device view showing more specific settings for each pair and channel. The device view shows one pair of the AD9094 at a time.  The **ADC Pair Selection** drop down box is used to select the current pair.  To select the desired pair (Pair AB or Pair CD) select the desired pair from the drop down box.  This sets the current changes to affect the select pair only.  The settings can now be configured for each channel.  Once the settings are configured click **Apply Changes** in the upper left of the device view.  This will load the setting changes to the selected ADC pair and channel(s). If the settings are desired for all four channels then click the **Apply** button in the **AD9094 Configuration** window on the left of the screen.  This loads the current settings to all channels in the device.{{ :resources:eval:9094_ace_device_view_read_all.png?link |}}<WRAP centeralign>//Pair AB - Channel A and Channel B NSR Settings (click to enlarge)//</WRAP>
     - The device view in ACE also has controls for the analog input controls.  The input buffer current, input full-scale voltage, and analog input differential termination can be adjusted.  The analog inputs can also be disabled from this menu. {{ :resources:eval:9094_ace_device_view_analog_input_controls.png?nolink |}}<WRAP centeralign>//Analog Input Control Settings//</WRAP>     - The device view in ACE also has controls for the analog input controls.  The input buffer current, input full-scale voltage, and analog input differential termination can be adjusted.  The analog inputs can also be disabled from this menu. {{ :resources:eval:9094_ace_device_view_analog_input_controls.png?nolink |}}<WRAP centeralign>//Analog Input Control Settings//</WRAP>
     - The **Memory Map View** can be accessed from the AD9094 **Device View**.  The **Memory Map View** can be used to individually write registers in the AD9094.  **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed.  If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :resources:eval:9094_ace_memorymap_view.png?link |}}<WRAP centeralign>//Memory Map View (click to enlarge)//</WRAP>     - The **Memory Map View** can be accessed from the AD9094 **Device View**.  The **Memory Map View** can be used to individually write registers in the AD9094.  **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed.  If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :resources:eval:9094_ace_memorymap_view.png?link |}}<WRAP centeralign>//Memory Map View (click to enlarge)//</WRAP>
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     - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:6684_va_fft_saveas.png?nolink |}}<WRAP centeralign>//Saving the FFT//</WRAP>     - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:6684_va_fft_saveas.png?nolink |}}<WRAP centeralign>//Saving the FFT//</WRAP>
  
 +====== Troubleshooting Tips ======
 +=== EVALUATION BOARD ISN'T FUNCTIONING PROPERLY ===
 +  * It is possible that a board component has been rendered inoperable by ESD, removing a jumper during powered operation, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows:
 +
 +^  Domain  ^  Jumper  ^  Test Point  ^  Approx. Voltage  ^
 +|  AVDD_0P9  |  P307  |  TP303  |  0.95 V  |
 +|  AVDD_1P8  |  P308  |  TP304  |  1.80 V  |
 +|  AVDD_BUF  |  P309  |  TP305  |  2.50 V  |
 +|  DRVDD_0P9  |  P304  |  TP301  |  0.95 V  |
 +|  AVDD_1P8_PLL  |  P311  |  TP306  |  1.80 V  |
 +|  DVDD_0P9  |  P305  |  TP302  |  0.95 V  |
 +|  AVDD_1P8_SPI  |  P312  |  TP307  |  1.80 V  |
 +
 +  * If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F401 (next to P401), a component may have been damaged. This may have occurred from jumper or board removal while being actively powered (See the warning in the [[resources/eval/ad9094-1000ebz?#ace_setup|ACE Setup section]]). See the [[resources/eval/ad9094-1000ebz?do=#design_and_integration_files |Design Integration Files section]] for the schematic and/or bill of materials for the relevant components to test and/or replace.
 +
 +=== EVALUATION BOARD IS NOT COMMUNICATING WITH THE ADS7-V2 / NO SPI COMMUNICATION ===
 +  * Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (FPGA_DONE) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed.
 +  * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_0P9. On the ADS7-V2, the common mode voltage should be around 1.2 volts.
 +  * Check Test Point 307 - test point for the AVDD_1P8_SPI supply domain, jumper P312 - and make sure it is around 1.8 volts.
 +  * To test SPI operation, attempt to both read and write to register 0x000A using ACE's Register Debugger (View → Register Debugger). This register is an open register available for testing memory reads and writes. If the value written to this register does not reset after writing it, SPI is operational.
 +  * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.
 +  * Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed.
  
 +=== EVALUATION BOARD FAILS TO CAPTURE DATA ===
 +  * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.
 +  * Check the Clock Detect register 0x011B to see if the inputted clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator inputting on connector J203. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip.
 +  * Check the PLL Locked indicator or register 0x056F (PLL Status). If the light is green / if the register reads back 0x80, the PLL is locked. If it is not locked:
 +      * Check the clock being inputted to connector J203
 +      * Check the JESD settings under the Initial Configuration. Reference the [[adi>media/en/technical-documentation/data-sheets/ad9094.pdf|AD9094 datasheet]] for supported lane options.
 +      * Check the reference clock and make sure it matches your JESD settings.
 +      * Make sure P100 (Power Down / Standby Jumper) is not jumped.
resources/eval/ad9094-1000ebz.txt · Last modified: 23 Sep 2022 09:48 by James Peevee Salenga

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