This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
resources:eval:ad9083 [22 Feb 2021 22:14] – [Evaluation] Alex Arrants | resources:eval:ad9083 [05 Jan 2022 16:45] (current) – change Gerber layout files to layout files Brigid Duggan | ||
---|---|---|---|
Line 26: | Line 26: | ||
===== Board Design and Integration Files ===== | ===== Board Design and Integration Files ===== | ||
* {{: | * {{: | ||
- | * {{: | + | * {{: |
* {{: | * {{: | ||
Line 198: | Line 198: | ||
* fC = 800 MHz. | * fC = 800 MHz. | ||
* High Performance Mode = False | * High Performance Mode = False | ||
- | * fIn Max = 50 MHz (sample rate/20). | + | * Fin Max = 50 MHz (sample rate/20). |
* Backoff = 0 | * Backoff = 0 | ||
* # ADC Channels = 16 | * # ADC Channels = 16 | ||
Line 223: | Line 223: | ||
//Figure 9. AD9083EBZ Precision Time Domain Mode Typical FFT // | //Figure 9. AD9083EBZ Precision Time Domain Mode Typical FFT // | ||
+ | ===== External Trigger ===== | ||
+ | SMA connector J2 on the ADS8v3 can be used as an optional trigger so that the data capture start time can be controlled. The trigger requires a 1.8V active high pulse width that is longer than the FPGA internal peripheral clock, which has a frequency of 50 MHz. | ||
+ | To enable the external trigger: | ||
+ | |||
+ | 1. Click on " | ||
+ | {{: | ||
+ | |||
+ | 2. Click on the " | ||
+ | {{: | ||
+ | |||
+ | 3. Click on the " | ||
+ | {{: | ||
+ | |||
+ | 4. Click "Apply Changes" | ||
+ | {{: | ||
+ | |||
+ | SMA connector J3 is normally used as a system ready indicator. It indicates that the FPGA is ready to accept an external trigger. | ||
+ | |||
+ | To capture data, click on "Run Once" as normal. Capture will begin once 1.8V is detected on connector J2 of the ADS8v3. | ||
+ | |||
===== Troubleshooting Notes ===== | ===== Troubleshooting Notes ===== | ||
**Evaluation Board is not Functioning Properly** | **Evaluation Board is not Functioning Properly** |