This version (14 Jan 2021 05:15) was approved by Robin Getz.The Previously approved version (11 May 2017 22:16) is available.Diff



This user guide describes the AD6688-3000EBZ evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. This guide entails both the hardware and software setup needed to acquire data capture from the evaluation board. This guide assumes the usage of the accompanying ADS7-V2 EBZ High Speed Evaluation Board. The user guide for the ADS7-V2 provides additional information available for consultation during usage. Documents and software tools, where available, can be found at the HS-ADC Eval Board homepage. For additional information or questions, post a question on Engineer Zone, or send an email to

Typical Setup

Figure 1. AD6688-3000EBZ (Left) and ADS7-V2 (Right)

Figure 2. Top of AD6688-3000EBZ Board

Figure 3. Bottom of AD6688-3000EBZ Board

Tip: Click on any picture in this guide to open an enlarged version.
Tip: The AD6688-3000EBZ is the export-controlled version of the AD9208-3000EBZ. To see the wiki page for the 9208, click here.


  • Full featured evaluation board for the AD6688-3000EBZ.
  • JESD204B coded serial digital outputs with support for lane rates up to 16Gbps/lane.
  • Wide full power bandwidth supports IF sampling of signals up to 9GHz (-3dB point).
  • Four Integrated wide-band decimation filter and NCO blocks supporting multi-band receivers.
  • Fast NCO switching enabled through GPIO pins.
  • Flexible SPI interface controls various product features and functions to meet specific system requirements.
  • Programmable fast over range detection and signal monitoring.
  • On-chip temperature diode for system thermal management.

Helpful Documents

Software Needed

  • ACE (Analysis | Control | Evaluation)

Design and Integration Files

Equipment Needed

  • PC running Windows®
  • USB 2.0 port and USB 2.0 High-speed A to B Cable
  • AD6688-3000EBZ evaluation board
  • ADS7-V2EBZ FPGA-based data capture kit
  • 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ)
  • Low phase noise analog input source and antialiasing filter
  • Low phase noise sample clock source
  • Reference clock source

Getting Started

This section provides quick start procedures for using the AD6688 evaluation board.

Connector Layout

Figure 4. ADS7-V2 Connector Layout

Figure 5. AD6688-3000EBZ Connector Layout

Tip: For more information on Sysref and Global Clock (J3, J4, J200, J202), see the JESD204B Survival Guide.
Warning: The AD6688-3000EBZ is electrostatic discharge (ESD) sensitive. Handle the device with care, and employ conducting wrist straps or antistatic bags when handling the board.

Configuring the Board

Figure 6. Jumper connections on AD6688-3000EBZ

Before using the software for testing, configure the evaluation boards as follows:

  1. Before connecting the AD6688 to the ADS7-V2, jump the following pins: P304, P305, P307, P308, P309, P311, and P312. Do not jump P7 (Temperature Sensor Enable) or P100 (Power Down / Standby). Jump P401 towards the inside of the board, to power the board via FMC. See Figure 6 for all jumper connections.
  2. Ensure that the data capture board is switched to “OFF.” (S1 on the data capture board) Connect the evaluation board to the data capture board via the FMC connector found on the underside of the board, as shown in Figure 1. Connect the power supply and USB cable to the data capture board.
  3. Turn on the ADS7-V2EBZ.
  4. The ADS7-V2EBZ should appear in the Device Manager as shown in Figure 7.

    Figure 7. Device Manager showing ADS7-V2EBZ

  5. If the Device Manager does not show the ADS7-V2EBZ listed as shown in Figure 7, unplug all USB devices from the PC, uninstall and re-install ACE and restart the hardware setup from step 1.
  6. On the AD6688 evaluation board, provide a clean, low jitter 3 GHz clock source to connector J201 (preferably via a shielded RG-58 50 Ω coaxial cable) and set the amplitude to 10 dBm. This is the ADC Sample Clock.
  7. On the ADS7-V2, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10 dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:

    LaneLineRate=M*Nprime*(10/8)*f_{out}/Lbps/lane, where

    f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio

    Nprime=8 or 16

    REFCLK = LaneLineRate/20

    (Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes)

  8. On the AD6688 evaluation board, connect a clean signal generator with low phase noise to J101 or J104 via coaxial cable for channels A and B respectively. It is recommended to use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency.

ACE Setup

  1. Download and install ACE if it is not already installed.
  2. The AD6688 ACE plug-in can be found under the 6688 Evaluation Board Software Section or through ACE's Plug-In Manager (Tools → Manage Plug-Ins).
    Tip: Some browsers (Such as Internet Explorer) may save the file as a .zip file instead of an .acezip file. If this happens, simply download and rename the file with an .acezip file extension.
  3. Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install.
  4. Click Start → All Programs → Analog Devices → ACE → ACE
  5. The AD6688 plug-in should appear as in Figure 8 if successfully installed.
  6. If the AD6688 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.

    Figure 8. ACE's AD6688 Plug-in

    Note: Differences may occur between ACE plug-in versions, including the version number seen in Figure 8 above or components in any of the other images below - however, these will not affect the performance of the part nor the fundamental features described in this user guide.
  7. Click on the plug-in to open it. This will automatically program the FPGA.
    Warning: Programming the FPGA will power the AD6688 evaluation board via the FMC connector. Removing any of the board's power jumpers (as seen in Figure 6) while the board is on or in operation may cause damage to the board, board components, and/or the chip. Removing the board while it is being powered via the FMC connector may also cause damage to the board.

    Figure 9. AD6688 Chip View

Obtaining a Full Bandwidth Capture

Tip: The AD6688-3000EBZ is the export-controlled version of the AD9208-3000EBZ. Because of this, the AD6688-3000EBZ is only able to operate in 7-bit mode for full bandwidth captures. To take full captures with the AD6688-3000EBZ, see the section below on DDCs. To see the 14-bit full bandwidth operation, see the page for the 9208.

Obtaining a DDC Capture

  1. This section explains the steps needed to setup the AD6688-3000EBZ in a DDC (Decimal Down Converter) setup as shown in Figure 10.

    Figure 10. AD6688 DDC Setup Block Diagram

  2. Under Initial Configuration, set the Chip Operating Mode for two DDCs. The DDC settings will become available, and automatically set up for Decimate-by-4 mode. For the decimation, select “HB1_HB2_HB3 Complex” - three half-band filters, i.e. Decimate-by-8. Set the number of lanes to 4, the number of converters to 4, and the number of Octets per Frame to 2. Apply the settings.

    Figure 11. DDC Chip Settings

    Figure 12. Apply Settings

  3. The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the Read All button.

    Figure 13. Read All

  4. Issue a data path reset to the AD6688 by clicking its checkbox and clicking Apply Changes. The data path reset bit will automatically self clear.

    Figure 14. Data path reset

    Figure 15. Apply Changes

  5. If the PLL Lock Lost indicator lights up, you can reset it by powering down the JESD link using the Link Control dropdown box, and clicking Apply Changes.

    Figure 16. PLL Lock Lost

    Figure 17. Link Power Down

  6. Enable the link again and Apply Changes.

    Figure 18. Link Enable

  7. Click on the NCO block to change the Noise Controlled Oscillator's frequency to 1300 MHz. Enable the 6dB gain for the DDC from the dropdown menu. Click Apply Changes to apply both.

    Figure 19. NCO Frequency Setting

    Figure 20. DDC Gain

  8. Navigate to the second DDC (DDC1) and make the same changes.

    Figure 21. DDC Selection

  9. Click Proceed to Analysis. This is ACE's Analysis tool for data from the ADC, displaying both sample plots and FFTs. Click on DDCFFT and run one capture.

    Figure 22. Analysis Tool

    Figure 23. Display FFTs

    Figure 24. Run one capture

    Tip: Capturing data using another program (e.g. VisualAnalog, proprietary code, etc.) while using ACE concurrently may cause errors in ACE's data capture. If this occurs, the best solution is to restart the evaluation boards and work solely via ACE, or to setup the part in ACE then capture solely in the other program.
  10. DDC0 can be selected from Channel A and DDC1 can be selected from Channel B.

    Figure 25. DDC Selection

  11. A successful capture is shown below, with a filtered 1305 MHz signal inputted on Channel A / DDC0.

    Figure 26. Example Input to DDC0

Troubleshooting Tips


  • It is possible that a board component has been rendered inoperable by ESD, removing a jumper during powered operation, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows:
Domain Jumper Test Point Approx. Voltage
AVDD_1 P307 TP303 0.975 V
AVDD_2 P308 TP304 1.90 V
AVDD_3 P309 TP305 2.50 V
DRVDD_1 P304 TP301 0.975 V
DRVDD_2 P311 TP306 1.90 V
DVDD P305 TP302 0.975 V
SPI_VDD P312 TP307 1.90 V
  • If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F401 (next to P401), a component may have been damaged. This may have occurred from jumper or board removal while being actively powered (See the warning in the ACE Setup section). See the Design Integration Files section for the schematic and/or bill of materials for the relevant components to test and/or replace.


  • Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (FPGA_DONE) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed.
  • Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts.
  • Check Test Point 307 - test point for the SPI_VDD supply domain, jumper P312 - and make sure it is around 1.9 volts.
  • To test SPI operation, attempt to both read and write to register 0x000A using ACE's Register Debugger (see Figure 23). This register is an open register available for testing memory reads and writes. If the value written to this register does not reset after writing it, SPI is operational.
  • All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.
  • Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed.


  • Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.
  • Check the Clock Detect register 0x011B to see if the inputted clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator inputting on connector J201. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip.
  • Check the PLL Locked indicator (see Figure 16) or register 0x056F (PLL Status). If the light is green / if the register reads back 0x80, the PLL is locked. If it is not locked:
    • Check the clock being inputted to connector J201 (in this guide, 3 GHz).
    • Check the JESD settings under the Initial Configuration. Reference the AD6688 datasheet for supported lane options.
    • Check the reference clock and make sure it matches your JESD settings.
    • Make sure P100 (Power Down / Standby Jumper, see Figure 6) is not jumped.
resources/eval/ad6688-3000ebz.txt · Last modified: 14 Jan 2021 05:11 by Robin Getz