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resources:eval:ad6684-500ebz [25 Feb 2019 16:14] – [ACE Setup] Alan Yu | resources:eval:ad6684-500ebz [14 Jan 2021 05:11] (current) – user interwiki links Robin Getz | ||
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===== Software Needed ===== | ===== Software Needed ===== | ||
* VisualAnalog [[ftp:// | * VisualAnalog [[ftp:// | ||
- | * ACE [[https:// | + | * ACE [[/ |
===== Design and Integration Files ===== | ===== Design and Integration Files ===== | ||
- | *[[https:// | + | * {{ :eval:9694_board_files_ce04.zip |AD9694CE04A schematic, BOM, layout files}} |
===== Equipment Needed ===== | ===== Equipment Needed ===== | ||
* Analog signal source and antialiasing filter | * Analog signal source and antialiasing filter | ||
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- The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ : | ||
- If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | ||
- | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector | + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector |
- | - On the ADC evaluation | + | - On the [[ads7-v2|ADS7-V2EBZ]] data capture |
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J106. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J107. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
==== Visual Analog Setup ==== | ==== Visual Analog Setup ==== | ||
- Click Start < | - Click Start < | ||
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- Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). {{ : | - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). {{ : | ||
- If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ : | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ : | ||
- | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | + | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked. |
- Click **OK** | - Click **OK** | ||
==== ACE Setup ==== | ==== ACE Setup ==== | ||
- Click Start < | - Click Start < | ||
- Once ACE opens the AD6684 evaluation board should appear in the **Attached Hardware** section. {{ : | - Once ACE opens the AD6684 evaluation board should appear in the **Attached Hardware** section. {{ : | ||
- | - Double click on the **AD6684 Eval Board** icon which will open up the Initial Configuration wizard. The default conditions for the AD6684 are NSR mode with a sample clock of 500 MHz. From here both pairs of ADC channels (Pair AB and Pair CD) can be configured simultaneously. | + | - Double click on the **AD6684 Eval Board** icon which will open up the Initial Configuration wizard. The default conditions for the AD6684 are NSR mode with a sample clock of 500 MHz. From here both pairs of ADC channels (Pair AB and Pair CD) can be configured simultaneously. |
- Prior to configuring any modes in the AD6684 double click on the **AD6684** icon to bring up the device view. From the device view click on the **Read All** icon to read the SPI settings from the device. | - Prior to configuring any modes in the AD6684 double click on the **AD6684** icon to bring up the device view. From the device view click on the **Read All** icon to read the SPI settings from the device. | ||
- From the the **Initial Configuration Wizard** the clock frequency, chip application mode (per pair), DDC inputs and outputs, and the JESD204B settings can be quickly configured. The default conditions are: | - From the the **Initial Configuration Wizard** the clock frequency, chip application mode (per pair), DDC inputs and outputs, and the JESD204B settings can be quickly configured. The default conditions are: |