| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:eval:ad6684-500ebz [05 May 2017 17:06] – [Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode] Judy Chui | resources:eval:ad6684-500ebz [14 Jan 2021 05:11] (current) – user interwiki links Robin Getz |
|---|
| The [[adi>AD6684|AD6684]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. | The [[adi>AD6684|AD6684]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. |
| ===== AD6684 Evaluation Board ===== | ===== AD6684 Evaluation Board ===== |
| | The images below show the location and position of the jumpers on the old (first image) and new (second image) versions of the [[adi>AD6684|AD6684-500EBZ]]. |
| {{ :resources:eval:ad9694_jumpers.jpg?direct800 |}}<WRAP centeralign> | {{ :resources:eval:ad9694_jumpers.jpg?direct800 |}}<WRAP centeralign> |
| //[[adi>AD6684|AD6684]] Evaluation Board//</WRAP> | //[[adi>AD6684|AD6684]] Evaluation Board//</WRAP> |
| | {{ :resources:eval:ad9694_jumpers_new_board.jpg?direct800 |}}<WRAP centeralign> |
| | //[[adi>AD6684|AD6684]] Evaluation Board (new version)//</WRAP> |
| ===== Typical Measurement Setup ===== | ===== Typical Measurement Setup ===== |
| The [[adi>AD6684|AD6684-500EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figure below shows the [[adi>AD6684|AD6684-500EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]]. | The [[adi>AD6684|AD6684-500EBZ]] can be evaluated using the [[ads7-v2|ADS7-V2EBZ]] FPGA data capture board. The figure below shows the [[adi>AD6684|AD6684-500EBZ]] connected to the [[ads7-v2|ADS7-V2EBZ]]. If using the old version of the board, refer to the first image for connections, otherwise if using the new version of the board, refer to the second image. |
| {{ :resources:eval:ad9694_connection.png?direct&800 |}}<WRAP centeralign> | {{ :resources:eval:ad9694_connection.png?direct&800 |}}<WRAP centeralign> |
| //Evaluation Board Connection—[[adi>AD6684|AD6684-500EBZ]]// | //Evaluation Board Connection—[[adi>AD6684|AD6684-500EBZ]]// |
| | </WRAP> |
| | {{ :resources:eval:ad9694_connection_new_board.jpg?direct&800 |}}<WRAP centeralign> |
| | //(New) Evaluation Board Connection—[[adi>AD6684|AD6684-500EBZ]]// |
| </WRAP> | </WRAP> |
| ===== Features ===== | ===== Features ===== |
| ===== Software Needed ===== | ===== Software Needed ===== |
| * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]] | * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]] |
| * ACE [[https://wiki.analog.com/resources/tools-software/ace]] | * ACE [[/resources/tools-software/ace]] |
| ===== Design and Integration Files ===== | ===== Design and Integration Files ===== |
| *[[https://wiki.analog.com/_media/eval/9694_board_files_ce01.zip|AD9694CE01A schematic, BOM, layout files]] | * {{ :eval:9694_board_files_ce04.zip |AD9694CE04A schematic, BOM, layout files}} |
| ===== Equipment Needed ===== | ===== Equipment Needed ===== |
| * Analog signal source and antialiasing filter | * Analog signal source and antialiasing filter |
| - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP> | - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager.{{ :resources:eval:9694_ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP> |
| - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. |
| - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock. | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J204 and set the amplitude to 14dBm. This is the ADC Sample Clock. |
| - On the ADC evaluation board, provide a clean, low jitter clock source to connector J201 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP> | - On the [[ads7-v2|ADS7-V2EBZ]] data capture board, provide a clean, low jitter clock source to connector J3 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:<WRAP centeralign> <m> LaneLineRate=M*Nprime*(10/8)*f_{out}/L </m>bps/lane, where </WRAP><WRAP centeralign> <m> f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16 </m>//(Default Nprime = 16)//</WRAP><WRAP centeralign> <m> REFCLK = LaneLineRate/20 </m></WRAP> |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD6684 make sure the clock source has a 50% duty cycle. For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source. | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J101. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) If providing an input clock with a divide-by-1 setting in the AD6684 make sure the clock source has a 50% duty cycle. For optimum SNR performance use the clock divider with a divide ratio of 2 or higher to minimize the impact of the phase noise from the input clock source. |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel C to J104. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J106. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel D to J107. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) |
| ==== Visual Analog Setup ==== | ==== Visual Analog Setup ==== |
| - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog | - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> VisualAnalog <m>right</m> VisualAnalog |
| - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). {{ :resources:eval:9694_data_capture_settings_general.png?nolink |}} <WRAP centeralign>//Changing the ADC Capture Settings//</WRAP> | - Click the **General** button in the **ADC Data Capture Settings** block. On the **General** tab make sure the clock frequency is set to 2x the input clock. For example, if the input clock to the AD6684 is 368.64 MHz then set the **Clock Frequency (MHz)** to 737.28 MHz. The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel). {{ :resources:eval:9694_data_capture_settings_general.png?nolink |}} <WRAP centeralign>//Changing the ADC Capture Settings//</WRAP> |
| - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP> | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Expanding Display in VA//</WRAP> |
| - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is checked. |
| - Click **OK** | - Click **OK** |
| ==== ACE Setup ==== | ==== ACE Setup ==== |
| - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> ACE <m>right</m> ACE | - Click Start <m>right</m> All Programs <m>right</m> Analog Devices <m>right</m> ACE <m>right</m> ACE |
| - Once ACE opens the AD6684 evaluation board should appear in the **Attached Hardware** section. {{ :resources:eval:6684_ace_start.png?nolink |}}<WRAP centeralign>//ACE Attached Hardware: AD6684 //</WRAP> | - Once ACE opens the AD6684 evaluation board should appear in the **Attached Hardware** section. {{ :resources:eval:6684_ace_start.png?nolink |}}<WRAP centeralign>//ACE Attached Hardware: AD6684 //</WRAP> |
| - Double click on the **AD6684 Eval Board** icon which will open up the Initial Configuration wizard. The default conditions for the AD668 are NSR mode with a sample clock of 500 MHz. From here both pairs of ADC channels (Pair AB and Pair CD) can be configured simultaneously. **NOTE:It is important to remember that the AD6684 functions as two dual ADCs.** {{ :resources:eval:6684_ace_initial_config.png?nolink |}}<WRAP centeralign>//ACE - AD6684 Initial Configuration Wizard//</WRAP> | - Double click on the **AD6684 Eval Board** icon which will open up the Initial Configuration wizard. The default conditions for the AD6684 are NSR mode with a sample clock of 500 MHz. From here both pairs of ADC channels (Pair AB and Pair CD) can be configured simultaneously. **NOTE: It is important to remember that the AD6684 functions as two dual ADCs.** {{ :resources:eval:6684_ace_initial_config.png?nolink |}}<WRAP centeralign>//ACE - AD6684 Initial Configuration Wizard//</WRAP> |
| - Prior to configuring any modes in the AD6684 double click on the **AD6684** icon to bring up the device view. From the device view click on the **Read All** icon to read the SPI settings from the device. Do this for each pair by selecting one pair at a time and then clicking the **Read All** icon.{{ :resources:eval:6684_ace_device_view_nsr_read_all.png?nolink |}}<WRAP centeralign>//ACE - AD6684 Initial Configuration Wizard//</WRAP> | - Prior to configuring any modes in the AD6684 double click on the **AD6684** icon to bring up the device view. From the device view click on the **Read All** icon to read the SPI settings from the device. Do this for each pair by selecting one pair at a time and then clicking the **Read All** icon.{{ :resources:eval:6684_ace_device_view_nsr_read_all.png?nolink |}}<WRAP centeralign>//ACE - AD6684 Initial Configuration Wizard//</WRAP> |
| - From the the **Initial Configuration Wizard** the clock frequency, chip application mode (per pair), DDC inputs and outputs, and the JESD204B settings can be quickly configured. The default conditions are: | - From the the **Initial Configuration Wizard** the clock frequency, chip application mode (per pair), DDC inputs and outputs, and the JESD204B settings can be quickly configured. The default conditions are: |
| - The **Memory Map View** can be accessed from the AD6684 **Device View**. The **Memory Map View** can be used to individually write registers in the AD6684. **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed. If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :resources:eval:6684_ace_memorymap_view.png?nolink |}}<WRAP centeralign>//Memory Map View//</WRAP> | - The **Memory Map View** can be accessed from the AD6684 **Device View**. The **Memory Map View** can be used to individually write registers in the AD6684. **Note: When writing individual registers it is imperative to first write the Pair Index register (0x0009) before any other write so that the correct ADC channel pair (Pair AB or Pair CD) is being addressed. If writing a local register, subsequently write the ADC channel index register (0x0008) so that the desired channel within the desired pair is written (Channel A/C or Channel B/D).** {{ :resources:eval:6684_ace_memorymap_view.png?nolink |}}<WRAP centeralign>//Memory Map View//</WRAP> |
| ==== Obtaining an FFT - NSR Mode ==== | ==== Obtaining an FFT - NSR Mode ==== |
| - Using the AD6684_Quad_Normal_FFT.vac canvas file, the first item to configure in Visual Analog is the input clock frequency. This needs to be set to twice the frequency of the input clock. Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :resources:eval:9694_data_capture_settings_general.png?nolink |}}<WRAP centeralign>//AD6684 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This needs to be set to twice the frequency of the input clock. Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :resources:eval:9694_data_capture_settings_general.png?nolink |}}<WRAP centeralign>//AD6684 FFT Data Capture Settings//</WRAP> |
| - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6684. Under Advanced Calculation, click the Enable box, select AD6674 NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings. {{ :resources:eval:6684_va_fftanalysis_nsr.png?nolink |}}<WRAP centeralign>//AD6684 FFT Analysis NSR Settings//</WRAP> | - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6684. Under Advanced Calculation, click the Enable box, select AD6674 NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings. {{ :resources:eval:6684_va_fftanalysis_nsr.png?nolink |}}<WRAP centeralign>//AD6684 FFT Analysis NSR Settings//</WRAP> |
| - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). | - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). |
| - The VDR mode (complex/real), bandwidth (25%/43%), and tuning word can be configured from the **Device View** in ACE. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. In this example a real input signal is used so the tuning word and mode must be changed. See the AD6674 data sheet for more details on the available bandwidth modes and tuning words. To access the device view, double-click the **AD6684** icon from the **AD6684 Eval Board** view which will bring up the view below. In this example VDR is set to **Dual Real 25% BW Mode** with the tuning word set to 6. Once the settings have been entered click **Apply Changes** in the upper left of the **Device View**. This will apply changes to the ADC Pair (Pair AB or Pair CD) selected in the **Device View**. To do so, set the **ADC Pair Selection** to the desired pair, configure the block diagram as desired and click **Apply Changes** in the upper left of the window. This should be done for each pair (Pair AB and Pair CD). {{ :resources:eval:6684_ace_device_view_vdr.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B VDR Settings//</WRAP> | - The VDR mode (complex/real), bandwidth (25%/43%), and tuning word can be configured from the **Device View** in ACE. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. In this example a real input signal is used so the tuning word and mode must be changed. See the AD6674 data sheet for more details on the available bandwidth modes and tuning words. To access the device view, double-click the **AD6684** icon from the **AD6684 Eval Board** view which will bring up the view below. In this example VDR is set to **Dual Real 25% BW Mode** with the tuning word set to 6. Once the settings have been entered click **Apply Changes** in the upper left of the **Device View**. This will apply changes to the ADC Pair (Pair AB or Pair CD) selected in the **Device View**. To do so, set the **ADC Pair Selection** to the desired pair, configure the block diagram as desired and click **Apply Changes** in the upper left of the window. This should be done for each pair (Pair AB and Pair CD). {{ :resources:eval:6684_ace_device_view_vdr.png?nolink |}}<WRAP centeralign>//Pair AB: Channel A and Channel B VDR Settings//</WRAP> |
| ==== Obtaining an FFT - VDR Mode ==== | ==== Obtaining an FFT - VDR Mode ==== |
| - Using the AD6684_Quad_Normal_FFT.vac canvas file, the first item to configure in Visual Analog is the input clock frequency. This needs to be set to twice the frequency of the input clock. Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :resources:eval:9694_data_capture_settings_general.png?nolink |}}<WRAP centeralign>//AD6684 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This needs to be set to twice the frequency of the input clock. Click in the ADC Data Capture block to open the settings. In this example, 368.64 MHz is the input clock frequency so 737.28 is entered into VisualAnalog.{{ :resources:eval:9694_data_capture_settings_general.png?nolink |}}<WRAP centeralign>//AD6684 FFT Data Capture Settings//</WRAP> |
| - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). | - In this example, with an input clock of 368.64MHz, the output sample rate is 368.64MSPS. The default JESD204B lane configuration for the JESD204B link of each ADC Channel Pair is 2.2.2 (L.M.F). The required REFCLK frequency is 368.64 MHz (refer to step 7 in the section "Configuring the Board"). |
| - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:6684_vdr_fft_tw6_fin150mhz.png?800 |}}<WRAP centeralign>//AD6684 FFT with VDR Enabled (Tuning Word = 6//</WRAP> | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:6684_vdr_fft_tw6_fin150mhz.png?800 |}}<WRAP centeralign>//AD6684 FFT with VDR Enabled (Tuning Word = 6//</WRAP> |
