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| resources:eval:ad6679-500ebz [23 Apr 2015 21:50] – [Troubleshooting Tips] Jonathan Harris | resources:eval:ad6679-500ebz [17 Nov 2022 03:32] (current) – [Troubleshooting Tips] John Xavier Toledo |
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| ====== EVALUATING THE AD6679 IF DIVERSITY RECEIVER ====== | ====== EVALUATING THE AD6679 IF DIVERSITY RECEIVER ====== |
| ===== Preface ===== | ===== Preface ===== |
| This user guide describes the [[adi>AD6679|AD6679]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. | This user guide describes the [[adi>AD6679|AD6679]] evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. The [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] is the recommended FPGA based data capture board for the [[adi>AD6679|AD6679]]. The [[adi>eval-ads7-v2|ADS7-V2EBZ]] may alternatively be used as the FPGA based data capture board for the [[adi>AD6679|AD6679]]. |
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| The [[adi>AD6679|AD6679]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. | The [[adi>AD6679|AD6679]] data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. For additional information or questions, send an email to highspeed.converters@analog.com. |
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| ===== AD6679 Evaluation Board ===== | ===== AD6679 Evaluation Board ===== |
| {{ :resources:eval:ad9684_conenctions.jpg?direct600 |}}<WRAP centeralign> | {{ :resources:eval:ad9684evb.jpg?direct600 |}}<WRAP centeralign> |
| //Figure 1. [[adi>AD6679|AD6679]] Evaluation Board//</WRAP> | //Figure 1. [[adi>AD6679|AD6679]] Evaluation Board//</WRAP> |
| |
| ===== Typical Measurement Setup ===== | ===== Typical Measurement Setup ===== |
| {{ :resources:eval:ad9684_setup2.jpg?direct&600 |}}<WRAP centeralign> | {{ :resources:eval:ad9684_evalez_setup.jpg?direct&600 |}}<WRAP centeralign> |
| //Figure 2. Evaluation Board Connection—[[adi>AD6679|AD6679-500EBZ (on Left) and [[ads7-v2|ADS7-V2EBZ]] (on Right)// | //Figure 2. Evaluation Board Connection—[[adi>AD6679|AD6679-500EBZ]] (on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] (on Right)// |
| </WRAP> | </WRAP> |
| ===== Features ===== | ===== Features ===== |
| ===== Helpful Documents ===== | ===== Helpful Documents ===== |
| * [[adi>AD6679|AD6679]] Data Sheet | * [[adi>AD6679|AD6679]] Data Sheet |
| * ADS7-V2EBZ evaluation kit ([[ads7-v2|ADS7-V2EBZ]]) | * [[adi>hsadcevalboard|HSC-ADC-EVALEZ]], //HSC-ADC-EVALEZ Evaluation Kit// |
| | * [[adi>eval-ads7-v2|ADS7-V2EBZ]], ADS7-V2 Evaluation Kit (optional) |
| * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// | * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// |
| * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software// | * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software// |
| * [[>resources/technical-guides/adispi>|ADI SPI Application Note]] // ADI Serial Control Interface Standard// | * [[adi>an-877|AN-877 Application Note]], //Interface to High-Speed ADCs via SPI// |
| * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation// | * [[adi>an-835|AN-835 Application Note]], //Understanding ADC Testing and Evaluation// |
| | * [[adi>media/en/technical-documentation/application-notes/AN-1371.pdf|AN-1371 Application Note]], //Variable Dynamic Range// |
| |
| ===== Software Needed ===== | ===== Software Needed ===== |
| * VisualAnalog [[ftp://ftp.analog.com/pub/HSSP_SW/VisualAnalog/VisualAnalog_Setup.exe]] | * [[adi>en/design-center/interactive-design-tools/visualanalog.html | VisualAnalog]] |
| * SPIController [[ftp://ftp.analog.com/pub/adispi/A2DComponents/Install/SPIController_Setup.exe]] | * [[adi>en/design-center/interactive-design-tools/spicontroller.html | SPIController ]] |
| ===== Design and Integration Files ===== | ===== Design and Integration Files ===== |
| * ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ | * Schematic: {{ :resources:eval:ad6679_sch.pdf | AD6679 Rev A}} |
| * FPGA BIN file [[ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ad9684_ads7v2.bin]] | * Layout: {{ :resources:eval:ad6679_lay.pdf | AD6679 Rev A}} |
| | * Bill of Materials: {{ :resources:eval:ad6679_bom.xlsx | AD6679 Rev A}} |
| | * FPGA MCS file (EVALEZ): {{ :resources:eval:ad9684_evalez_05202014_0903am.zip}} |
| | * FPGA MCS file (ADS7-V2): {{ :resources:eval:ad9684_ads7v2.zip}} |
| ===== Equipment Needed ===== | ===== Equipment Needed ===== |
| * Analog signal source and antialiasing filter | * Analog signal source and antialiasing filter |
| * Sample clock source | * Sample clock source |
| * 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with [[ads7-v2|ADS7-V2EBZ]]) | * 12V, 6.5A switching power supply (supplied with the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] or the SL POWER CENB1080A1251F01 supplied with [[adi>eval-ads7-v2|ADS7-V2EBZ]]) |
| * PC running Windows® | * PC running Windows® |
| * USB 2.0 port | * USB 2.0 port |
| * [[adi>AD6679|AD6679-500EBZ]] board | * [[adi>AD6679|AD6679-500EBZ]] board |
| * [[ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit | * [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] FPGA-base data capture kit |
| | * [[adi>eval-ads7-v2|ADS7-V2EBZ]] FPGA-based data capture kit (optional, but not required - if an [[adi>eval-ads7-v2|ADS7-V2EBZ]] has been previously purchased for use with other ADI ADCs then it may be also be used for the [[adi>AD6679|AD6679-500EBZ]]) |
| |
| ===== Getting Started ===== | ===== Getting Started ===== |
| ==== Configuring the Board ==== | ==== Configuring the Board ==== |
| Before using the software for testing, configure the evaluation board as follows: | Before using the software for testing, configure the evaluation board as follows: |
| - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]] data capture board, as shown in Figure 2. | - Connect the evaluation board to the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] data capture board, as shown in Figure 2. |
| - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]] board. Connect the Standard-B USB port of the [[ads7-v2|ADS7-V2EBZ]] board to the PC with the supplied USB cable. | - Connect one 12V, 6.5A switching power supply to P1301 on the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] board. Connect the Standard-B USB port of the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] board to the PC with the supplied USB cable. |
| - Turn on the [[ads7-v2|ADS7-V2EBZ]]. | - The [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] will appear in the Device Manager as shown in Figure 3.{{ :resources:eval:evalez_devmgr.png?nolink&300 |}}<WRAP centeralign>//Figure 3. Device Manager showing [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]//</WRAP> |
| - The [[ads7-v2|ADS7-V2EBZ]] will appear in the Device Manager as shown in Figure 3.{{ :resources:eval:ads7v2_devmgr.png?nolink&300 |}}<WRAP centeralign>//Figure 3. Device Manager showing [[ads7-v2|ADS7-V2EBZ]]//</WRAP> | - If the Device Manager does not show the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. |
| - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]] listed as shown in Figure 2, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1. | |
| - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock. |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.) |
| - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 5. Expanding Display in VA//</WRAP> | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5){{ :resources:eval:fig4_expand_display.png?nolink |}}<WRAP centeralign>//Figure 5. Expanding Display in VA//</WRAP> |
| - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure 6 {{ :resources:eval:AD6679_capture_settings.png?600 |}}<WRAP centeralign>//Figure 6. Changing the ADC Capture Settings//</WRAP> | - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure 6 {{ :resources:eval:AD6679_capture_settings.png?600 |}}<WRAP centeralign>//Figure 6. Changing the ADC Capture Settings//</WRAP> |
| - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADs7-V2 FPGA software supports up to 2M FFT capture (1M per channel){{ :resources:eval:AD6679_capture_settings.png?600 |}}<WRAP centeralign>//Figure 7. Setting the clock frequency and Capture length//</WRAP> | - On the **General** tab make sure the clock frequency is set to **500MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The HSC-ADC-EVALEZ FPGA software supports up to 2M FFT capture (1M per channel){{ :resources:eval:AD6679_capture_settings.png?600 |}}<WRAP centeralign>//Figure 7. Setting the clock frequency and Capture length//</WRAP> |
| - Click on the **Capture Board** tab and browse to the **ad9684_ads7v2.bin** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the ADS7-V2 board indicating that the FPGA has been correctly programmed. The bin file is available at the ftp site [[ftp://ftp.analog.com/pub/HSC_ADC_Apps/AD9684CE01A_Design_Support/ad9684_ads7v.bin]] | - Click on the **Capture Board** tab and browse to the **ad9684_evalez_05202014_0903am.mcs** file. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the HSC-ADC-EVALEZ board indicating that the FPGA has been correctly programmed. |
| - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | |
| - Click **OK** | - Click **OK** |
| ==== SPIController Setup ==== | ==== SPIController Setup ==== |
| ==== Obtaining an FFT - NSR Mode ==== | ==== Obtaining an FFT - NSR Mode ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 12. AD6679-500 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 12. AD6679-500 FFT Data Capture Settings//</WRAP> |
| - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6679. Under Advanced Calculation, click the Enable box, select AD6679 NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings. {{ :resources:eval:AD6679_fftanalysis_nsr_settings.png?nolink |}}<WRAP centeralign>//Figure 13. AD6679-500 FFT Analysis NSR Settings//</WRAP> | - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6679. Under Advanced Calculation, click the Enable box, select [[adi>ad6679|AD6679]] NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings. {{ :resources:eval:AD6679_fftanalysis_nsr_settings.png?nolink |}}<WRAP centeralign>//Figure 13. AD6679-500 FFT Analysis NSR Settings//</WRAP> |
| - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD6679_fft_nsr.png?800 |}}<WRAP centeralign>//Figure 14. AD6679-500 FFT with NSR Enabled//</WRAP> | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD6679_fft_nsr.png?800 |}}<WRAP centeralign>//Figure 14. AD6679-500 FFT with NSR Enabled//</WRAP> |
| - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in the FFT in Visual Analog. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in the FFT in Visual Analog. |
| ==== Device Setup - VDR Mode ==== | ==== Device Setup - VDR Mode ==== |
| - The default Chip Application Mode for the AD6679 is set to NSR. The settings in the ADCBase0 tab must be changed to configure the AD6679 into VDR mode. To set up the AD6679 for VDR mode change the Chip Application Mode in register 0x200 to Variable Dynamic Range (VDR) Mode and set the Chip Decimation Ratio in register 0x201 to Full Sample Rate. {{ :resources:eval:AD6674_spi_vdr_adcglobal.png?800 |}}<WRAP centeralign>//Figure 17. Set Application Mode to VDR//</WRAP> | - The default Chip Application Mode for the AD6679 is set to NSR. The settings in the ADCBase0 tab must be changed to configure the AD6679 into VDR mode. To set up the AD6679 for VDR mode change the Chip Application Mode in register 0x200 to Variable Dynamic Range (VDR) Mode and set the Chip Decimation Ratio in register 0x201 to Full Sample Rate. {{ :resources:eval:AD6674_spi_vdr_adcglobal.png?800 |}}<WRAP centeralign>//Figure 17. Set Application Mode to VDR//</WRAP> |
| - The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). See the AD6679 data sheet for more details on the available bandwidth modes and tuning words. {{ :resources:eval:AD6674_spi_vdr_tuningword.png?300 |}}<WRAP centeralign>//Figure 18. Channel A and Channel B VDR Settings//</WRAP> | - The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to **25% Bandwidth Complex Mode** with a **Tuning Word of 0**. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). See the AD6679 data sheet for more details on the available bandwidth modes and tuning words. {{ :resources:eval:AD6674_spi_vdr_tuningword.png?300 |}}<WRAP centeralign>//Figure 18. Channel A and Channel B VDR Settings//</WRAP> |
| ==== Obtaining an FFT - VDR Mode ==== | ==== Obtaining an FFT - VDR Mode ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 19. AD6679-500 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 19. AD6679-500 FFT Data Capture Settings//</WRAP> |
| - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 21. Floating the FFT window//</WRAP> | - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 21. Floating the FFT window//</WRAP> |
| - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD6679_fft_graph_saveformas.png?nolink |}}<WRAP centeralign>//Figure 22. Saving the FFT//</WRAP> | - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD6679_fft_graph_saveformas.png?nolink |}}<WRAP centeralign>//Figure 22. Saving the FFT//</WRAP> |
| ==== Setting up SPIController to Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== | ==== Setting up SPIController to Output the VDR High/Low Resolution Bit or the VDR Punish Bit - VDR Mode ==== |
| - The first step go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits. In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit.{{ :resources:eval:AD6679_spi_vdr_bits_adcbase2.png?nolink |}}<WRAP centeralign>//Figure 26. SPIController ADCBase2 Settings for VDR Indicators in the Control Bits//</WRAP> | - To enable the VDR High/Low Resolution bit go to the ADCBase2 tab in SPIController. In the OUTPUT CTRL MODE REG(559) drop down select "VDR High/Low Resolution Bit".{{ :resources:eval:AD6679_spi_vdr_highlowbit_adcbase2.png?nolink |}}<WRAP centeralign>//Figure 26. SPIController ADCBase2 Settings for VDR High/Low Resolution Bit on Status Pins//</WRAP> |
| - Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits. In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.{{ :resources:eval:AD6679_spi_vdr_bits_adcbase4.png?nolink |}}<WRAP centeralign>//Figure 27. SPIController ADCBase4 Settings for Enabling the Control Bits//</WRAP> | - Alternatively, the VDR Punish Bit can be enabled. To enable this bit go to ADCBase2 in SPIController and in the OUTPUT CTRL MODE REG(559) drop down select "Fast Detect (FD) or VDR Punish Bit {{ :resources:eval:AD6679_spi_vdr_punishbit_adcbase2.png?nolink |}}<WRAP centeralign>//Figure 27. SPIController ADCBase2 Settings for VDR Punish Bit on Status Pins//</WRAP> |
| ==== Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== | ==== Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== |
| - The first step is to open a new Logic canvas in VisualAnalog. In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits. This will create the space such that the VDR status bit can be visible in the Logic canvas.{{ :resources:eval:AD6674_va_inputformatter.png?nolink |}}<WRAP centeralign>//Figure 28. Input Formatter Settings for VDR Indicators in the Status Bit//</WRAP> | - The first step is to open a new Logic canvas in VisualAnalog. In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits. This will create the space such that the VDR status bit can be visible in the Logic canvas.{{ :resources:eval:AD6674_va_inputformatter.png?nolink |}}<WRAP centeralign>//Figure 28. Input Formatter Settings for VDR Indicators in the Status Bit//</WRAP> |
| - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Decimate by 4 Filter Selection (when in real mode this actually sets the AD6679 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Decimate by 4 Filter Selection (when in real mode this actually sets the AD6679 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 |
| - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcbase1.png?650 |}}<WRAP centeralign>//Figure 34. Channel A and Channel B DDC Settings//</WRAP> | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2ddcrealdec2_adcbase1.png?650 |}}<WRAP centeralign>//Figure 34. Channel A and Channel B DDC Settings//</WRAP> |
| - Using the default lane configuration in the AD6679 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | |
| ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD6679 so this must be selected under the ADC Data Capture Settings.{{ :resources:eval:AD6679_2ddcrealdec2_datacapturesettings.png?nolink |}}<WRAP centeralign>//Figure 35. AD6679-500 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD6679 so this must be selected under the ADC Data Capture Settings.{{ :resources:eval:AD6679_2ddcrealdec2_datacapturesettings.png?nolink |}}<WRAP centeralign>//Figure 35. AD6679-500 FFT Data Capture Settings//</WRAP> |
| - The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | - The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. |
| - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 40. DDC Settings for Complex ZIF Mode//</WRAP> | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 40. DDC Settings for Complex ZIF Mode//</WRAP> |
| - Using the default lane configuration in the AD6679 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | |
| ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD6679 so this must be selected under the ADC Data Capture Settings.{{ :resources:eval:AD6679_1ddccomplexdec2_datacapturesettings.png?nolink |}}<WRAP centeralign>//Figure 41. AD6679-500 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD6679 so this must be selected under the ADC Data Capture Settings.{{ :resources:eval:AD6679_1ddccomplexdec2_datacapturesettings.png?nolink |}}<WRAP centeralign>//Figure 41. AD6679-500 FFT Data Capture Settings//</WRAP> |
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| ** The FFT window remains blank after the Run button is clicked ** | ** The FFT window remains blank after the Run button is clicked ** |
| * Make sure the evaluation board is securely connected to the ADS7-V2. | * Make sure the evaluation board is securely connected to the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]]. |
| * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the ADS7-V2. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V2 setup process. | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]]. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the [[adi>eval-hsc-adc-evalez|HSC-ADC-EVALEZ]] setup process. |
| * Make sure the correct FPGA //bin// file was used to program the FPGA. | * Make sure the correct FPGA //bin// file was used to program the FPGA. |
| * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, and verify that the **Clock Frequency** is properly set.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 47. Setting the correct clock frequeency in VisualAnalog//</WRAP> | * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, and verify that the **Clock Frequency** is properly set.{{ :resources:eval:AD6679_capture_settings.png?nolink |}}<WRAP centeralign>//Figure 47. Setting the correct clock frequency in VisualAnalog//</WRAP> |
| * Restart SPIController. | * Restart SPIController. |
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| ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** |
| * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 48.{{ :resources:eval:AD6679_clockdetect.png?nolink |}}<WRAP centeralign>//Figure 48. Clock Detection Status Register//</WRAP> | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 48.{{ :resources:eval:AD6679_clockdetect.png?nolink |}}<WRAP centeralign>//Figure 48. Clock Detection Status Register//</WRAP> |
| * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController. | |
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