The EVAL-AD4630-24FMCZ, EVAL-AD4030-24FMCZ & EVAL-AD4630-16FMCZ evaluation boards enable quick and easy evaluation of the AD4X3X family of 24-bit & 16-bit precision successive approximation register (SAR) analog-to-digital converters (ADCs).
The AD4630-24 & AD4630-16 are 2MSPS per channel, low power, dual channel 24-bit or 16-bit SAR ADCs while the AD4030-24 is a single channel 24-bit precision SAR ADC that supports up to 2 MSPS per channel. The evaluation boards demonstrates the performance of either the AD4630-24, AD4030-24 or AD4630-16 and provides a configurable analog front end (AFE) for a variety of system applications.
The evaluations board are designed for use with the Digilent ZedBoard. The ZedBoard is used to control data capture and buffering. The evaluation board connects to the ZedBoard board via a field-programmable gate array (FPGA) mezzanine card (FMC) low pin count (LPC) connector. The ZedBoard hosts a Xilinx Zynq7000 SoC, which has two processor cores and programmable FPGA fabric. The ZedBoard connects to the PC through USB.
The evaluation board includes:
Full descriptions of these products are available in their respective data sheets, which should be consulted when using the evaluation board.
The installer can also be run from within ACE by clicking the link found in the 'IIIO Resources' section found in the Help » Application Resources section.
If there is a need to re-image or create a new SD card, instructions are available here: ADI Kuiper Linux with support for ACE Evaluation.
To avoid potential damage, ensure the VADJ SELECT jumper is set to the correct voltage for the Product Evaluation Board.
There may be additional steps and hardware required for a given Product Evaluation Board, for example, function generators connections and setup. This information may be included with the eval kit or in the User guide for the corresponding Product Evaluation Boards page that can be found by searching Product Evaluation Boards and Kits.
Figure 1. EVAL-AD4630-XXFMCZ Evaluation System
Figure 2a. EVAL-AD4030-24FMCZ
Figure 1 illustrates the evaluation system components. To use the system, connect the evaluation board to the ZedBoard, connect a micro-USB cable to the USB OTG port, apply power to the ZedBoard, open the ACE GUI, and supply an input stimulus to one or both ADC channels.
Each ADC channel has dedicated SMA connectors that support either a singled-ended or differential input. The signals on these inputs are injected to the configurable AFE (see the Analog Front End section below for more details). The digital interface to the system controller board uses level shifters to translate between the VIO supply of the AD4630-16 and the I/O voltage of the Zynq 7000 on the ZedBoard. By default, the evaluation board is powered from the system controller board 12V supply through the FMC connector. The Power Supplies section contains a list of optional on-board connections that can be used to connect external supplies and references to the board.
The primary 12 volt supply to the EVAL-AD4X30-XXFMCZ comes from the ZedBoard through the FMC connector. 12 volts is regulated down to an intermediate voltage with a switcher and then is post regulated down to the various voltage rails. 12 volts is also used to generate the negative rails for the buffers and final drive amplifiers.
Each of the voltage rails are brought out to turrets so they can be easily measured (see Figure 1). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the AD4630-24 datasheet, AD4030-24 datasheet or AD4630-16 datasheet should be consulted to ensure that the external supply values comply with the device requirements.
|Power Supply||Function||Min. (V)||Max. (V)|
|+12V||12 volt primary supply via FMC connector||N/A||N/A|
|+3.3V||3.3 volts for various digital logic||3.26||3.33|
|+1.8V||1.8 volts for the ADC||1.77||1.81|
|VIO||1.8 volt supply for the ADC digital I/O||1.8||1.87|
|+5V||5 volts for the ADC||5.26||5.4|
|REFIN||5 volt ADC reference input||4.95||5.05|
|VAMP+||Positive supply for the amplifiers||5.36||5.47|
|VAMP-||Negative supply for the amplifiers||-3.5||-3.28|
|VP1||5.7 volts at the input of the switcher||5.45||5.75|
|REF||5 volts at the ADC reference output||4.95||5.05|
|EN||1.8 volts enable signal for the power supplies||1.75||1.85|
Table 1. On-Board Power Supplies
By default, the on-board LT6655 provides a 5 V reference to the AD4630-24, AD4030-24 & AD4630-16. It drives the REFIN pin of the ADC through an R-C filter (R=100Ω, C=1μF) that reduces the low frequency noise. The REFIN pin is connected to an internal buffer, eliminating the need for an external buffer. However, if the user desires to use an external reference that drives the internal buffer, it can be attached the EXT REF SMA connector (see figure below). R137 should be populated with a zero ohm resistor, and R136 should be open. The internal buffer can be bypassed by attaching an external reference to the REF turret on the board. To reduce the ADC power consumption, the internal reference buffer can be disabled (see respective products data sheet).
Figure 3. EVAL-AD4X30-XXFMCZ Reference circuit (AD4630-24 shown. Configuration applies to all parts)
The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4630-24, AD4030-24 or AD4630-16. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4X30-XXFMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R55 and connect an external clock source to J1, the CLK IN SMA. The external clock frequency must be < 100 MHz. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm.
Figure 4. EVAL-AD4X30-XXFMCZ clock circuit (AD4630-24 shown. Configuration applies to all parts)
The EVAL-AD4X30-XXFMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 5, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. Note: As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity.
Figure 5. Differential Driver AFE (default) (AD4630-24 shown. Configuration applies to all parts)
|Function:||Single ended to differential via differential amplifier|
|Required changes from default configuration:||No changes required|
Table 2. EVAL-AD4620-16FMCZ Default AFE Configuration
A second topology can be seen in Figure 6. This topology consists of a pair of unity gain buffers, the ADA4896-2. It also can be driven by either a singled-ended or differential source. This network is ideal for observing the best noise performance of the AD4630-16, due to the low voltage and current noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers a common mode input impedance of 10 MΩ and a wide input common mode voltage range of -4.9V to +4.1V (when using +/- 5V supplies). Note: This driver circuit also inverts the polarity of the input signal. To preserve polarity when measuring DC voltages, connect a positive voltage to IN_A/B-. Likewise, a negative DC voltage should be connected to IN_A/B+.
Figure 6. Dual Buffer AFE (AD4630-24 shown. Configuration applies to all parts)
|Function:||Differential input using buffer amplifiers|
|Comments:||Best noise & relaxed drive requirement for signal source|
|Required changes from default configuration:||Remove: R10, R12,R119, R120, R121 & R122 (Ch. A); R20, R22, R123, R124, R125 & R126 (Ch. B). Install: R31, R33, R47, & R49 (Ch. A); R60, R62, R75 & R78 (Ch. B)|
Table 3. Unity Gain Dual Buffer Configuration
Figure 7 shows a driver network which combines the ADA4896-2 with the ADA4945-1. This circuit is ideal for applications that require a high input impedance along with gain to maximize the input range of the ADC. The gain of the ADA4945-1 can modified by changing either the feedback resistors or input resistors.
Figure 7. High Impedance Buffer with Gain AFE (AD4630-24 shown. Configuration applies to all parts)
|Function:||High impedance input with gain|
|Comments:||Relaxed drive requirements from signal source plus signal scaling.|
|Required changes from default configuration:||Remove:R120, R121 (Ch. A);R124, R125 (Ch. B). Install: R31, R127, R28, R47, R128 & R43 (Ch. A); R60, R129, R57, R78, R130 & R72 (Ch. B)|
Table 4. High Impedance with Gain Configuration
Figure 8 shows an input configuration that allows the AD4630-16 to be directly driven from the SMA connectors. This enables testing with alternative driver configurations mounted on an external PCB.
Figure 8. Direct Driven Inputs (AD4630-24 shown. Configuration applies to all parts)
|Function:||Direct input path|
|Comments:||Supports evaluation with an alternative driver|
|Required changes from default configuration:||Remove: R10, R12, R119 & R122 (Ch A); R20, R22, R123, R126 (Ch B). Install: R28, R29, R120, R121, R43 & R44 (Ch A); R124, R57, R58, R125, R72 & R73 (Ch B)|
Table 5. Direct Drive Configuration
The ZedBoard, which is the system controller board, enables the configuration of the ADC and capture of data from the evaluation board by the PC via USB (or Ethernet). The AD4X30-XX family of parts support a multi-lane serial port interface (SPI) for each data converter channel. The SPI interface for each channel is connected to the ZedBoard via the FMC connector (P1). The ZedBoard™ functions as the communication link between the PC and connected evaluation board. It buffers samples captured from the evaluation board in its DDR3 memory. The ZedBoard board requires power from a 12 volt wall adapter (included with the ZedBoard). It hosts a Xilinx® ZYNQ® 7020 SoC, which contains two ARM® Cortex-A9 Processors and a Series-7 FPGA with 85k Programmable Logic cells. A Linux OS runs on the host processor system. It communicates with the PC through either a USB 2.0 high speed port or a 10/100/1000 Ethernet port. The default software configuration uses USB.
The ACE evaluation software controls and configures the evaluation board through the ZedBoard.
Before connecting the evaluation board to the ZedBoard, take the following steps to set up the AD4630-24, AD4030-24 or AD4630-16 for initial use in the ACE evaluation software:
1. Download the ACE evaluation software package from the ACE software page to start the ACE evaluation software installation.
2. Click on Download ACE Installer to download the file.
3. Run the installer and follow the instructions to complete the software installation process.
During the installation process, be sure to select Precision Converter Components when prompted and enable the LibIIO Wrapper to ensure that all necessary software components are installed.
Figure 9. Select Precision Converter Components during the ACE installation
When the following prompt appears, be sure to select LibIIO and LibIIODrivers options, then click Install.
Figure 10. Select LibIIO components during ACE installation
When the ACE evaluation software installation is complete, take the following steps to set up the ZedBoard and the evaluation board together:
1. Insert the SD card provided with the evaluation board into J12 on the ZedBoard
2. Connect the Evaluation board to the FMC connector of the ZedBoard.
3. Connect the provided power supplies to J20 on the ZedBoard.
4. Connect the USB cable to the USB OTG (J13) on the ZedBoard and to the computer
5. Connect the desired input signal to the appropriate input on the evaluation board (J2-J5)
6. Move SW8 to the ON position to start the ZedBoard
7. Start the ACE evaluation software (see the Software Operation section).
To start the ACE evaluation software, from the Windows Start menu, click Analog Devices > ACE. The software window opens (see Figure 11) until the software recognizes the AD4630-24, AD4030-24 or AD4630-16 evaluation board. When the software recognizes the board, double-click on the icon in the Start view to open the main window seen in Figure 12. For more detailed information about ACE, refer to the ACE user guide: Analysis | Control | Evaluation - ACE Software
Figure 11. Select Interface Window
Figure 12. ACE Evaluation Software Main Window
In the main ACE evaluation software window (see Figure 12), the AD4630-16 can be configured. Various settings for the AD4630-24, AD4030-24 or AD4630-16 are available in this window, including the number of SPI data lanes (lane mode), clock mode, data rate, and data mode (sample format).
Select the number of SPI lanes to use to transmit the data. The options are 1, 2, or 4 lanes per channel.
Selects between the echo clock mode and the SPI clock mode.
Selects between single data rate (SDR: 1-bit per clock cycle) or dual data rate (DDR: 2-bits per clock cycle). DDR is only available when using Echo clock mode or Master clock mode. Note: The current Linux driver and HDL do not support Master clock mode.
Selects the data output format of the AD4630-24, AD4030-24 or AD4630-16. The available formats are: 24-bit differential data with 8 bit common mode (AD4630-24 & AD4030-24), 24-bit differential data (AD4630-24 & AD4030-24) or 16 bit differential data (AD4630-16), 16-bit differential data and 8 bit common mode, 30-bit averaged data, or a 32-bit programmable test pattern.
Changes to the operating parameters listed above requires a reboot of the ZedBoard. By clicking Apply Operating mode and reboot, the ACE software will configure the part and load the correct FPGA image. It will also automatically reset the ZedBoard. The specific steps include:
1. After changing any of the operating parameters, click “Apply Operating mode and reboot”.
2. Close any of the following ACE windows that may be open:
3. Click on the “Home” icon in the upper portion of the left pane. The AD4630 plug-in should appear. If not, it may be necessary to click Refresh Attached Hardware
4. Double-click on the part plug-in to open the board view and start using the available evaluation functions.
Figure 14. Chip View
By clicking on the part in the main ACE evaluation software window (see Figure 12), the chip view will be opened (Figure 14). Settings for the part available in this window include enabling and configuring averaging mode, changing the sample frequency, and changing the gain and offset for each channel. Refer to the data sheet for a detailed explanation of these features.
Selects between normal operating mode and low power mode.
Sets the number of samples to be used by the internal block averaging filter of the part. Select OFF to disable averaging, or select the desired number of samples to be averaged by the part. Ensure that the Data Mode is set to 30-bit averaged data when using this feature.
Selects the desired sample frequency from a drop down menu. Note that this is the frequency of the pulse that is applied to the CNV pin. The sampling frequency can be scaled by changing the frequency of the reference clock (see the Clock Circuit section). The sampling rate selected from the menu can be scaled by applying a lower frequency external clock. The effective sampling rate is: selected sampling frequency x fEXT/100 MHz.
If the block averaging filter is enabled, the effective output sample rate is the sampling frequency divided by the selected block average size.
This sets the internal digital gain applied to the differential data. The gain can be adjusted independently for each channel.
This sets the internal digital offset that is applied to the differential data. The offset can be independently set for each channel.
Figure 15. Register Map
By clicking on Proceed to Memory Map in the lower right corner of the Chip view (see Figure 12), the AD4630 register map view will be opened (figure 15). In this view all registers can be read and selected registers can be modified. Changes to the register contents can be written to the part by clicking Apply Changes. Under normal operation no changes are necessary to the register map. Registers that change the operating mode should not be changed in this view.
Figure 16. Analysis View
By clicking on Proceed to Analysis in the lower right corner of the Chip view (see Figure 12), the Analysis view will open (Figure 16). In the CAPTURE pane the desired capture block size is entered in the Sample Count text box. At the bottom of the CAPTURE pane, select Run Once to capture a single block, or select Run Continuously to enable continuous updates. Data will be collected and plotted as a time domain waveform (Figure 17), an FFT (Figure 18), or a histogram (Figure 19) by selecting the desired view on the left side of the CAPTURE pane. The RESULTS pane displays parametric values for the selected display format. The user can pan and zoom on the plot area. Various data sets can be selected in the top right corner of the plot area. The bottom of the RESULTS pane also has buttons that allow the user to import or export sample data.
Figure 17. Time domain waveform
Figure 18. FFT view
Figure 19. Histogram view
The following table illustrates the maximum sampling rates that can be achieved based on the device configuration. Note that the FPGA SPI engine only supports Zone 2 data transfers from the AD4630/AD4030.
Table 3. Maximum sampling rate by device configuration
|Clocking Mode||Lane Mode (per channel)||Data Rate||Data format||Max sampling rate|
|SPI||1||Single (SDR)||32-bit||1.75 MSPS (note 1)|
|Dual (DDR)||32 or 24-bit||2 MSPS|
|2||SDR or DDR||32 or 24-bit||2 MSPS|
|4||SDR or DDR||32 or 24-bit||2 MSPS|
|Echo Clock||1||SDR||32-bit||1.75 MSPS (note 1)|
|DDR||32 or 24-bit||2 MSPS|
|2||SDR or DDR||32 or 24-bit||2 MSPS|
|4||SDR or DDR||32 or 24-bit||2 MSPS|
Note 1: The sampling rate in Single lane, 32-bit output formats in SDR mode are limited by the FPGA SPI engine. This is not a limitation of the AD4630/AD4030 device.
Analog Devices supports the development of custom applications using the EVAL-AD4X30-XX system and are described in the AD463x and AD403x Developer's Guide
Technical support for the evaluation board hardware and software can be obtained by posting a question to ADI's EngineerZone technical support community for precision ADCs.
The evaluation board schematic and other board files can be found on the EVAL-AD4630-16FMCZ, EVAL-AD4630-24FMCZ & EVAL-AD0630-24FMCZ web pages.
A troubleshooting guide can be found at: Troubleshooting Guide for ADI Kuiper Linux for ACE Evaluation. The latter covers some tips related to ZedBoard startup and the SD card containing the Kuiper Linux image.