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resources:eval:ad4030-24-eval-board [13 Apr 2022 21:25] – [Analog Front End] Clarence MAYOTTresources:eval:ad4030-24-eval-board [20 Jul 2022 16:03] (current) – test Padraic O Reilly
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-====== AD4030-24 SAR ADC Evaluation Board User Guide ====== +{{section>resources/eval/ad4630-24-eval-board&showfooter=nofooter}}
-===== General Description ===== +
- +
-The EVAL-AD4030-24FMCZ evaluation board enables quick and easy evaluation of the AD4030 family of 24-bit precision successive approximation register (SAR) analog-to-digital converters (ADCs). \\  +
-The [[http://www.analog.com/en/products/AD4030-24.html|AD4030-24]] is a low power, 24-bit precision SAR ADC that supports up to 2 MSPS. The evaluation board demonstrates the performance of the AD4030-24 and provides a configurable analog front end (AFE) for a variety of system applications. \\  +
-The EVAL-AD4030-24FMCZ evaluation board is designed for use with the Digilent [[http://digilent.com/shop/zedboard-zynq-7000-arm-fpga-soc-development-board/|ZedBoard]]. The ZedBoard is used to control data capture and buffering. The evaluation board connects to the ZedBoard board via a field-programmable gate array (FPGA) mezzanine card (FMC) low pin count (LPC) connector. The ZedBoard hosts a Xilinx Zynq7000 SoC, which has two processor cores and programmable FPGA fabric. The ZedBoard connects to the PC through USB. \\  +
-The evaluation board includes:\\  +
-  * A high precision buffered band gap 5 volt reference ([[https://www.analog.com/en/products/ltc6655.html|LTC6655]]). +
-  * An analog front end (AFE) that provides signal conditioning and drive for the AD4030-24. The AFE can be configured to use either the [[http://www.analog.com/en/products/ADA4896-2.html|ADA4896-2]] in a dual buffer configuration, or the [[http://www.analog.com/en/products/ADA4945-1.html|ADA4945-1]], a fully differential amplifier.  +
-  * An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +
-  * Full power supply solution that provides all the necessary voltage rails from a 12 volt supply that is provided from the ZedBoard through the FMC connector. \\  +
- +
-Full descriptions of these products are available in their respective data sheets, which should be consulted when using the evaluation board.\\  +
-===== Features ===== +
-  * On-board voltage reference, clock source, and ADC drivers +
-  * Versatile analog signal conditioning circuitry +
-  * FMC-LPC system board connector +
-  * ACE PC software for configuration and data analysis (time and frequency domain) +
-  * Compatible with other off-the-shelf controller boards +
-===== Evaluation Board Kit Contents ===== +
-  * EVAL-AD4030-24FMCZ evaluation board +
-  * Micro-SD memory card (with adapter) containing system board boot software and Linux OS +
-  * Optional - ZedBoard (system controller board ) +
- +
-===== Equipment Needed ===== +
-  * PC with Windows 7 or Windows 10 operating system +
-  * Digilent ZedBoard with 12 V wall adapter power supply +
-  * Precision signal source +
-  * SMA Cable(s) (input to evaluation board) +
-  * Recommended - Band-pass filter centered on test signal frequency. +
- +
-===== Quick Start Guide ===== +
-1. Download and install ACE Software from [[adi>en/design-center/evaluation-hardware-and-software/evaluation-development-platforms/ace-software.html|ACE]]. A PC running Windows 7 or later is required. \\  +
-2. Connect the EVAL-AD4030-24-FMCZ board and ZedBoard™ firmly together through the FMC Connector. \\  +
-3. Insert the SD card provided with the EVAL-AD4030-24FMCZ into the SD card slot of the ZedBoard™. \\  +
-4. Connect the ZedBoard™’s USB OTG port (next to PMOD connector JE1) to the PC via a micro-USB cable. \\  +
-5. Connect the 12 volt power adaptor to ZedBoard™ and slide the POWER switch (SW8) on the ZedBoard™ to the ON position.\\  +
-6. Verify that the Green POWER LED (LD13) and the Blue Done LED (LD12) on the ZedBoard™ turn on.\\  +
-7. Wait for the Red LED (LD7) on the ZedBoard™ to start blinking.\\  +
-8. Launch the ACE software from the Windows Start menu.\\  +
-  +
-===== Evaluation Board Hardware ===== +
-{{:resources:eval:52675_2.jpg?400|}}\\  +
-\\  +
-**Figure 1. EVAL-AD4030-24FMCZ** \\  +
- +
- +
- +
- +
-==== Setting Up the Evaluation Board ==== +
-Figure 1 illustrates the AD4030 evaluation board. To use the system, connect the evaluation board to the ZedBoard, connect a micro-USB cable to the USB OTG port, apply power to the ZedBoard, open the ACE GUI, and supply an input stimulus to the ADC.\\  +
- +
-The evaluation board has dedicated SMA connectors that support either a singled-ended or differential input. The signals on these inputs are injected to the configurable AFE (see the **Analog Front End** section below for more details). The digital interface to the system controller board uses level shifters to translate between the VIO supply of the AD4030-24 and the I/O voltage of the Zynq 7000 on the ZedBoard. By default, the evaluation board is powered from the system controller board 12V supply through the FMC connector. The **Power Supplies** section contains a list of optional on-board connections that can be used to connect external supplies and references to the board.\\  +
-==== Power Supplies ==== +
-The primary 12 volt supply to the EVAL-AD4030-24FMCZ comes from the ZedBoard through the FMC connector. 12 volts is regulated down to an intermediate voltage with a switcher and then is post regulated down to the various voltage rails. 12 volts is also used to generate the negative rails for the buffers and final drive amplifiers. +
- +
-Each of the voltage rails are brought out to turrets so they can be easily measured (see **Figure 1**). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the [[http://www.analog.com/en/products/AD4030-24.html|AD4030-24 data sheet]] should be consulted to ensure that the external supply values comply with the device requirements. +
- +
-=== Table 1. On-Board Power Supplies === +
-^ Power Supply     ^   Function                                        ^    Min. (V)  ^    Max. (V)  ^   +
-| +12V             | 12 volt primary supply via FMC connector          |  N/A         |  N/A         | +
-| GND              | Ground connection                                 |  N/A         |  N/A         | +
-| +3.3V            | 3.3 volts for various digital logic               |  3.26        |  3.33        | +
-| +1.8V            | 1.8 volts for the ADC                             |  1.77        |  1.81        | +
-| VIO              | 1.8 volt supply for the ADC digital I/O           |  1.8         |  1.87        | +
-| +5V              | 5 volts for the ADC                               |  5.26        |  5.4         | +
-| REFIN            | 5 volt ADC reference input                        |  4.95        |  5.05        | +
-| VAMP+            | Positive supply for the amplifiers                |  5.36        |  5.47        | +
-| VAMP-            | Negative supply for the amplifiers                |  -3.5        |  -3.28       | +
-| VP1              | 5.7 volts at the input of the switcher            |  5.45        |  5.75        | +
-| REF              | 5 volts at the ADC reference output               |  4.95        |  5.05        | +
-| EN               | 1.8 volts enable signal for the power supplies    |  1.75        |  1.85        | +
-==== Reference Circuit ==== +
-By default, the on-board LT6655 provides a 5 V reference to the AD4030-24. It drives the REFIN pin of the ADC through an R-C filter (R=100Ω, C=1μF) that reduces the low frequency noise. The REFIN pin is connected to an internal buffer, eliminating the need for an external buffer. However, if the user desires to use an external reference that drives the internal buffer, it can be attached the EXT REF SMA connector (see figure below). R137 should be populated with a zero ohm resistor, and R136 should be open. The internal buffer can be bypassed by attaching an external reference to the REF turret on the board. To reduce the ADC power consumption, the internal reference buffer can be disabled (see the AD4030-24 data sheet). \\  +
-=== Figure 3. EVAL-AD4030-24FMCZ Reference circuit === +
-{{:resources:eval:ad4030_ref.png?400|}} +
- +
-==== Clock Circuit ==== +
-The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4030-24. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4030-24FMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R55 and connect an external clock source to J1, the CLK IN SMA. **The external clock frequency must be __<__ 100 MHz**. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm. \\  +
-=== Figure 4. EVAL-AD4030-24FMCZ clock circuit === +
-{{:resources:eval:eval-ad4630-24_clk_ckt.png?400|}}\\  +
-==== Analog Front End ==== +
-The EVAL-AD4030-24FMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 5, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. **Note:** As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity. \\  +
-=== Figure 5. Differential Driver AFE  ===   +
-{{:resources:eval:ad4030_input_1.png?400|}}\\  +
-=== Table 2. EVAL-AD4620-24FMCZ Default AFE Configuration === +
- +
-^ Function:                                      | Single ended to differential via differential amplifier      |  +
-^ Comments:                                      | Best distortion                                              | +
-^ Required changes from default configuration:   | Remove: R31, R33, R47 and R49  Install (0ohm resistors): R10, R11, R12, R13                                         | +
- +
-A second topology can be seen in Figure 6. This topology consists of a pair of unity gain buffers, the ADA4896-2. It also can be driven by either a singled-ended or differential source. This network is ideal for observing the best noise performance of the AD4030-24, due to the low voltage and current noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers a common mode input impedance of 10 MΩ and a wide input common mode voltage range of -4.9V to +4.1V (when using +/- 5V supplies). **Note:** This driver circuit also inverts the polarity of the input signal. To preserve polarity when measuring DC voltages, connect a positive voltage to IN_A/B-. Likewise, a negative DC voltage should be connected to IN_A/B+. \\  +
-=== Figure 6. Dual Buffer AFE (default) ===   +
-{{:resources:eval:ad4030_input_2.png?400|}}\\  +
-=== Table 3. Unity Gain Dual Buffer Configuration === +
-^ Function:                                      | Differential input using buffer amplifiers      |  +
-^ Comments:                                      | Best noise & relaxed drive requirement for signal source | +
-^ Required changes from default configuration:   | No changes required | +
- +
-Figure 7 shows a driver network which combines the ADA4896-2 with the ADA4945-1. This circuit is ideal for applications that require a high input impedance along with gain to maximize the input range of the ADC. The gain of the ADA4945-1 can modified by changing either the feedback resistors or input resistors. \\  +
-=== Figure 7. High Impedance Buffer with Gain AFE === +
-{{:resources:eval:ad4030_input_3.png?400|}} \\  +
-=== Table 4. High Impedance with Gain Configuration === +
-^ Function:                                      | High impedance input with gain      |  +
-^ Comments:                                      | Relaxed drive requirements from signal source plus signal scaling. | +
-^ Required changes from default configuration:   | Remove: R33, R49  Install (0ohm resistors): R127, R128, R28, R43, R10, R11, R12, R13, | +
- +
-Figure 8 shows an input configuration that allows the AD4030-24 to be directly driven from the SMA connectors. This enables testing with alternative driver configurations mounted on an external PCB. \\  +
-=== Figure 8 ===   +
-{{:resources:eval:ad4030_input_4.png?400|}}\\  +
-=== Table 5. Direct Drive Configuration === +
-^ Function:                                      | Direct input path      |  +
-^ Comments:                                      | Supports evaluation with an alternative driver | +
-^ Required changes from default configuration:   | Remove:R31, R33, R47 and R49  Install (0ohm resistors): R120, R28, R29, R121, R43, R44| \\  +
- +
- +
-===== Controller Board ===== +
-The ZedBoard, which is the system controller board, enables the configuration of the ADC and capture of data from the evaluation board by the PC via USB (or Ethernet). The AD4030-24 supports a multi-lane serial port interface (SPI) for the data converter. The SPI interface is connected to the ZedBoard via the FMC connector (P1). The ZedBoard™ functions as the communication link between the PC and connected EVAL-AD4030-24FMCZ evaluation board. It buffers samples captured from the evaluation board in its DDR3 memory. The ZedBoard board requires power from a 12 volt wall adapter (included with the ZedBoard). It hosts a Xilinx® ZYNQ® 7020 SoC, which contains two ARM® Cortex-A9 Processors and a Series-7 FPGA with 85k Programmable Logic cells. A Linux OS runs on the host processor system. It communicates with the PC through either a USB 2.0 high speed port or a 10/100/1000 Ethernet port. The default software configuration uses USB. +
-===== Evaluation Software ===== +
-==== GETTING STARTED ==== +
-  +
-The ACE evaluation software controls and configures the AD4030-24 evaluation board through the ZedBoard. +
-==== SOFTWARE INSTALLATION PROCEDURES ==== +
- +
-Before connecting the AD4030-24 evaluation board to the ZedBoard, take the following steps to set up the AD4030 for initial use in the ACE evaluation software: +
- +
-1. Download the ACE evaluation software package from the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-development-platforms/ace-software.html|ACE]] software page to start the ACE evaluation software installation. +
- +
-2. Click on **Download ACE Installer** to download the file.\\  +
- +
-3. Run the installer and follow the instructions to complete the software installation process.\\  +
-\\   +
-During the installation process, be sure to select **//Precision Converter Components//** when prompted to ensure that all necessary software components are installed. \\  +
-\\  +
-{{:resources:eval:ad4630_ace_install_pct_components.png?400|}}\\  +
-**//Figure 9. Select Precision Converter Components during the ACE installation//**\\  +
-\\  +
-When the following prompt appears, be sure to select **//LibIIO//** and **//LibIIODrivers//** options, then click **//Install//**.\\  +
-\\  +
-{{:resources:eval:AD4630_ace_install_libiio.png?400|}}\\  +
-**//Figure 10. Select LibIIO components during ACE installation//** \\  +
- +
- +
-==== EVALUATION HARDWARE SETUP ==== +
-When the ACE evaluation software installation is complete, take the following steps to set up the ZedBoard and the AD4030 evaluation board together: +
- +
-1. Insert the SD card provided with the EVAL-AD4030-24FMCZ into J12 on the ZedBoard +
- +
-2. Connect the AD4030 Evaluation board to the FMC connector of the ZedBoard.  +
- +
-3. Connect the provided power supplies to J20 on the ZedBoard. +
- +
-4. Connect the USB cable to the USB OTG (J13) on the ZedBoard and to the computer +
- +
-5. Connect the desired input signal to the appropriate input on the AD4030 evaluation board (J2-J5) +
- +
-6. Move SW8 to the ON position to start the ZedBoard +
- +
-7. Start the ACE evaluation software (see the Software Operation section). +
- +
-==== SOFTWARE OPERATION ==== +
-To start the ACE evaluation software, from the Windows Start menu, click Analog Devices > ACE. The software window opens (see Figure 11) until the software recognizes the AD4030-24 evaluation board. When the software recognizes the AD4030-24, double-click on the icon in the **//Start//** view to open the main window seen in Figure 12.  For more detailed information about ACE, refer to the ACE user guide: [[:resources:tools-software:ace|Analysis | Control | Evaluation - ACE Software]] +
- +
-{{:resources:eval:ad4030_first_page.jpg?400|}} +
- +
-**//Figure 11. Select Interface Window//** +
- +
- +
- +
-==== MAIN WINDOW ==== +
- +
-{{:resources:eval:ad4030_board_view.jpg?400|}} +
- +
-**//Figure 12. ACE Evaluation Software Main Window//** +
- +
-In the main ACE evaluation software window (see Figure 12), the AD4030-24 can be configured.  Various settings for the AD4030 are available in this window, including the number of SPI data lanes (lane mode), clock mode, data rate, and data mode (sample format). +
-=== Lane Mode ===  +
-Select the number of SPI lanes to use to transmit the data.  The options are 1, 2, or 4 lanes.   +
-=== Clock Mode === +
-Selects between the echo clock mode and the SPI clock mode. +
-=== Date Rate === +
-Selects between single data rate (SDR: 1-bit per clock cycle) or dual data rate (DDR: 2-bits per clock cycle). DDR is only available when using Echo clock mode or Master clock mode. **Note:** The current Linux driver and HDL do not support Master clock mode. +
-=== Data Mode === +
-Selects the data output format of the AD4030-24.  The available formats are: 24-bit differential data with 8 bit common mode, 24-bit differential data, 16-bit differential data and 8 bit common mode, 30-bit averaged data, or a 32-bit programmable test pattern.  +
-  +
-=== Apply Operating mode and reboot === +
-Changes to the operating parameters listed above requires a reboot of the ZedBoard.  By clicking **//Apply Operating mode and reboot//**, the ACE software will configure the AD4030-24 and load the correct FPGA image.  It will also automatically reset the ZedBoard. The specific steps include: +
- +
-1. After changing any of the operating parameters, click “Apply Operating mode and reboot”. +
- +
-2. Close any of the following ACE windows that may be open: +
- +
-  * Analysis +
- +
-  * AD4030IIO +
- +
-  * AD4030IIO Board +
- +
-  * Start +
- +
-  * System - In this tab, close the subsystem box that contains the components shown in the following figure.\\  +
-{{:resources:eval:AD4030_ace_system_view.png?600|}}\\ +
-**//Figure 13. AD4030-24 Subsystem view//** \\  +
- +
-3. Click on the “Home” icon in the upper portion of the left pane. The AD4030 plug-in should appear. If not, it may be necessary to click **//Refresh Attached Hardware//** \\  +
-4.      Double-click on the AD4030-24 plug-in to open the board view and start using the available evaluation functions.  +
- +
- +
-==== Chip View ==== +
- +
-{{:resources:eval:ad4030_chip_view.jpg?400|}} +
- +
-**//Figure 14 Chip View//** \\  +
- +
-By clicking on the AD4030 in the main ACE evaluation software window (see Figure 12), the chip view will be opened (Figure 14). Settings for the AD4030 available in this window include enabling and configuring averaging mode, changing the sample frequency, and changing the gain and offset. Refer to the AD4030-24 data sheet for a detailed explanation of these features. +
- +
-=== Operating mode === +
-Selects between normal operating mode and low power mode.  +
-=== Sample Averaging === +
-Sets the number of samples to be used by the internal block averaging filter of the AD4030-24. Select OFF to disable averaging, or select the desired number of samples to be averaged by the AD4030. Ensure that the Data Mode is set to 30-bit averaged data when using this feature. +
-=== Sampling Frequency === +
-Selects the desired sample frequency from a drop down menu. Note that this is the frequency of the pulse that is applied to the CNV pin. The sampling frequency can be scaled by changing the frequency of the reference clock (see the Clock Circuit section). The sampling rate selected from the menu can be scaled by applying a lower frequency external clock. The effective sampling rate is: **selected sampling frequency x f<sub>EXT</sub>/100 MHz**. \\  +
-If the block averaging filter is enabled, the effective output sample rate is the sampling frequency divided by the selected block average size. +
-=== Hardware Gain === +
-This sets the internal digital gain applied to the differential data.   +
-=== Offset === +
-This sets the internal digital offset that is applied to the differential data.   \\  +
-\\  +
- +
- +
- +
-==== REGISTER MAP ==== +
- +
-{{:resources:eval:memory_map_view.png?600|}} +
- +
-**//Figure 15. AD4030 Register Map//** +
- +
-By clicking on **//Proceed to Memory Map//** in the lower right corner of the Chip view (see Figure 12), the AD4030 register map view will be opened (figure 15).  In this view all registers can be read and selected registers can be modified.  Changes to the register contents can be written to the AD4030-24 by clicking **//Apply Changes//**.  Under normal operation no changes are necessary to the register map.  **//__Registers that change the operating mode should not be changed in this view__.//**  +
- +
- +
-==== ANALYSIS VIEW ==== +
- +
-{{:resources:eval:analysis_view.png?600|}} +
- +
-**//Figure 16. Analysis View//** +
- +
-By clicking on **//Proceed to Analysis//** in the lower right corner of the Chip view (see Figure 12), the **//Analysis//** view will open (Figure 16).  In the **//CAPTURE//** pane the desired capture block size is entered in the **//Sample Count//** text box.  At the bottom of the CAPTURE pane, select **//Run Once//** to capture a single block, or select **//Run Continuously//** to enable continuous updates. Data will be collected and plotted as a time domain waveform (Figure 17), an FFT (Figure 18), or a histogram (Figure 19) by selecting the desired view on the left side of the **//CAPTURE//** pane.  The **//RESULTS//** pane displays parametric values for the selected display format. The user can pan and zoom on the plot area.  Various data sets can be selected in the top right corner of the plot area.  The bottom of the **//RESULTS//** pane also has buttons that allow the user to import or export sample data. +
- +
-{{:resources:eval:waveform_view.png?600|}} +
- +
-**//Figure 17. Time domain waveform//** +
- +
-{{:resources:eval:fft_view.png?600|}} +
- +
-**//Figure 18. FFT view//** +
- +
-{{:resources:eval:histogram_view.png?600|}} +
- +
-**//Figure 19. Histogram view//** +
- +
-===== EVAL-AD4030-24FMCZ Support ===== +
-Technical support for the EVAL-AD4030-24FMCZ hardware and software can be obtained by posting a question to ADI's [[ez>data_converters/precision_adcs|EngineerZone]] technical support community for precision ADCs. \\  +
-\\  +
-The evaluation board schematic and other board files can be found on the [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD4030-24.html|EVAL-AD4030-24FMCZ]] web page. +
- +
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resources/eval/ad4030-24-eval-board.txt · Last modified: 20 Jul 2022 16:03 by Padraic O Reilly

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