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resources:alliances:altera [19 Mar 2015 19:22] – [CED1Z] Kevin Goodspeedresources:alliances:altera [10 Feb 2020 10:24] – Fix broke links Stanca-Florina Pop
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 ==== BeMicro SDK/SDP Interposer ==== ==== BeMicro SDK/SDP Interposer ====
  
-The [[http://www.arrownac.com/solutions/adi_interposer/|System Demonstration Platform (SDP) Interposer]] connects various Analog Devices evaluation boards to Altera FPGAs found on the BeMicro SDK forming a hardware and software evaluation system. It’s designed for use with [[adi>sdp#exallist|ADI product evaluation boards]] and Circuits from the Lab™ [[adi>sdp#exallist|reference circuit evaluation boards]] that have the  [[/resources/eval/sdp/sdp-b/hardware_description#connector_pin_assignments|SDP connector]].+The [[https://www.arrow.com/en/products/adiinterposer/analog-devices/|System Demonstration Platform (SDP) Interposer]] connects various Analog Devices evaluation boards to Altera FPGAs found on the BeMicro SDK forming a hardware and software evaluation system. It’s designed for use with [[adi>sdp#exallist|ADI product evaluation boards]] and Circuits from the Lab™ [[adi>sdp#exallist|reference circuit evaluation boards]] that have the  [[/resources/eval/sdp/sdp-b/hardware_description#connector_pin_assignments|SDP connector]].
  
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 | [[adi>EVAL-AD5570SDZ]] | {{/resources/fpga/altera/bemicro/ad5570_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5570|ADI Reference Design]] \\ \\ The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up, when the supply voltages are changing, VOUT is clamped to 0 V via a low impedance path. | [[adi>AD5570]] | | [[adi>EVAL-AD5570SDZ]] | {{/resources/fpga/altera/bemicro/ad5570_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5570|ADI Reference Design]] \\ \\ The AD5570 is a single 16-bit serial input, voltage output DAC that operates from supply voltages of ±11.4 V up to ±16.5 V. Integral linearity (INL) and differential nonlinearity (DNL) are accurate to 1 LSB. During power-up, when the supply voltages are changing, VOUT is clamped to 0 V via a low impedance path. | [[adi>AD5570]] |
 | [[adi>EVAL-AD5629RSDZ]] | {{/resources/fpga/altera/bemicro/ad5629r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5629r|ADI Reference Design]] \\ \\ The AD5629R device is a low power, octal, 12-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5629R]] | | [[adi>EVAL-AD5629RSDZ]] | {{/resources/fpga/altera/bemicro/ad5629r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5629r|ADI Reference Design]] \\ \\ The AD5629R device is a low power, octal, 12-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5629R]] |
-| [[adi>EVAL-AD5668SDZ]] | {{/resources/fpga/altera/bemicro/ad5668_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5668|ADI Reference Design]] \\ \\ The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5668]] |+| [[adi>EVAL-AD5668]] | {{/resources/fpga/altera/bemicro/ad5668_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5668|ADI Reference Design]] \\ \\ The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5668]] |
 | [[adi>EVAL-AD5669RSDZ]] | {{/resources/fpga/altera/bemicro/ad5669r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5669r|ADI Reference Design]] \\ \\ The AD5669R device is a low power, octal, 16-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5669R]] | | [[adi>EVAL-AD5669RSDZ]] | {{/resources/fpga/altera/bemicro/ad5669r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5669r|ADI Reference Design]] \\ \\ The AD5669R device is a low power, octal, 16-bit, buffered voltage-output DACs. It operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. | [[adi>AD5669R]] |
 | [[adi>EVAL-AD5684RSDZ]] | {{/resources/fpga/altera/bemicro/ad5686r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5684r|ADI Reference Design]] \\ \\ The AD56849R is a low power, quad, 12-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The EVAL-AD5684R evaluation board is designed to help customers quickly prototype new AD5684R circuits and reduce design time. The board requires ±5 V supplies. These are used to power the output amplifier and Vref. | [[adi>AD5684R]] | | [[adi>EVAL-AD5684RSDZ]] | {{/resources/fpga/altera/bemicro/ad5686r_bemicro.png?150  }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad5684r|ADI Reference Design]] \\ \\ The AD56849R is a low power, quad, 12-bit buffered voltage output DACs. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The EVAL-AD5684R evaluation board is designed to help customers quickly prototype new AD5684R circuits and reduce design time. The board requires ±5 V supplies. These are used to power the output amplifier and Vref. | [[adi>AD5684R]] |
resources/alliances/altera.txt · Last modified: 05 Oct 2020 21:01 by Adrian Costina