FILE_TYPE = PXL_HDL_CENTRIC_STATE_FILE;
VERSION = PXL_HDL_CENTRIC_VERSION_1;
TIME = '16-Nov-2018 AT 13:37:46.00';

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '1';

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS-SRST#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS-SRST#';
PHY_SIGNAL = 'PS-SRST#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO01_500_QSPI0_SS_B';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO01_500_QSPI0_SS_B';
PHY_SIGNAL = 'PS_MIO01_500_QSPI0_SS_B';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO02_500_QSPI0_IO0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO02_500_QSPI0_IO0';
PHY_SIGNAL = 'PS_MIO02_500_QSPI0_IO0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO03_500_QSPI0_IO1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO03_500_QSPI0_IO1';
PHY_SIGNAL = 'PS_MIO03_500_QSPI0_IO1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO04_500_QSPI0_IO2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO04_500_QSPI0_IO2';
PHY_SIGNAL = 'PS_MIO04_500_QSPI0_IO2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO05_500_QSPI0_IO3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO05_500_QSPI0_IO3';
PHY_SIGNAL = 'PS_MIO05_500_QSPI0_IO3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO06_500_QSPI0_SCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO06_500_QSPI0_SCLK';
PHY_SIGNAL = 'PS_MIO06_500_QSPI0_SCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO07_500_USB_RESET_B';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO07_500_USB_RESET_B';
PHY_SIGNAL = 'PS_MIO07_500_USB_RESET_B';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO28_501_USB0_D4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO28_501_USB0_D4';
PHY_SIGNAL = 'PS_MIO28_501_USB0_D4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO29_501_USB0_DIR';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO29_501_USB0_DIR';
PHY_SIGNAL = 'PS_MIO29_501_USB0_DIR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO30_501_USB0_STP';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO30_501_USB0_STP';
PHY_SIGNAL = 'PS_MIO30_501_USB0_STP';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO31_501_USB0_NXT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO31_501_USB0_NXT';
PHY_SIGNAL = 'PS_MIO31_501_USB0_NXT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO32_501_USB0_D0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO32_501_USB0_D0';
PHY_SIGNAL = 'PS_MIO32_501_USB0_D0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO33_501_USB0_D1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO33_501_USB0_D1';
PHY_SIGNAL = 'PS_MIO33_501_USB0_D1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO34_501_USB0_D2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO34_501_USB0_D2';
PHY_SIGNAL = 'PS_MIO34_501_USB0_D2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO35_501_USB0_D3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO35_501_USB0_D3';
PHY_SIGNAL = 'PS_MIO35_501_USB0_D3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO36_501_USB0_CLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO36_501_USB0_CLK';
PHY_SIGNAL = 'PS_MIO36_501_USB0_CLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO37_501_USB0_D5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO37_501_USB0_D5';
PHY_SIGNAL = 'PS_MIO37_501_USB0_D5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO38_501_USB0_D6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO38_501_USB0_D6';
PHY_SIGNAL = 'PS_MIO38_501_USB0_D6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO39_501_USB0_D7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PS_MIO39_501_USB0_D7';
PHY_SIGNAL = 'PS_MIO39_501_USB0_D7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_ID';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_ID';
PHY_SIGNAL = 'USB_ID';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_N';
PHY_SIGNAL = 'USB_OTG_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_P';
PHY_SIGNAL = 'USB_OTG_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_VBUS_OTG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_VBUS_OTG';
PHY_SIGNAL = 'USB_VBUS_OTG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A0';
PHY_SIGNAL = 'DDR3_A0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A1';
PHY_SIGNAL = 'DDR3_A1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A10';
PHY_SIGNAL = 'DDR3_A10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A11';
PHY_SIGNAL = 'DDR3_A11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A12';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A12';
PHY_SIGNAL = 'DDR3_A12';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A13';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A13';
PHY_SIGNAL = 'DDR3_A13';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A2';
PHY_SIGNAL = 'DDR3_A2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A3';
PHY_SIGNAL = 'DDR3_A3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A4';
PHY_SIGNAL = 'DDR3_A4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A5';
PHY_SIGNAL = 'DDR3_A5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A6';
PHY_SIGNAL = 'DDR3_A6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A7';
PHY_SIGNAL = 'DDR3_A7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A8';
PHY_SIGNAL = 'DDR3_A8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A9';
PHY_SIGNAL = 'DDR3_A9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA0';
PHY_SIGNAL = 'DDR3_BA0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA1';
PHY_SIGNAL = 'DDR3_BA1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_BA2';
PHY_SIGNAL = 'DDR3_BA2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CAS#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CAS#';
PHY_SIGNAL = 'DDR3_CAS#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CK_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CK_N';
PHY_SIGNAL = 'DDR3_CK_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CK_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CK_P';
PHY_SIGNAL = 'DDR3_CK_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CKE';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CKE';
PHY_SIGNAL = 'DDR3_CKE';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CS#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_CS#';
PHY_SIGNAL = 'DDR3_CS#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DM0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DM0';
PHY_SIGNAL = 'DDR3_DM0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DM1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DM1';
PHY_SIGNAL = 'DDR3_DM1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ0';
PHY_SIGNAL = 'DDR3_DQ0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ1';
PHY_SIGNAL = 'DDR3_DQ1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ10';
PHY_SIGNAL = 'DDR3_DQ10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ11';
PHY_SIGNAL = 'DDR3_DQ11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ12';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ12';
PHY_SIGNAL = 'DDR3_DQ12';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ13';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ13';
PHY_SIGNAL = 'DDR3_DQ13';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ14';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ14';
PHY_SIGNAL = 'DDR3_DQ14';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ15';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ15';
PHY_SIGNAL = 'DDR3_DQ15';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ2';
PHY_SIGNAL = 'DDR3_DQ2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ3';
PHY_SIGNAL = 'DDR3_DQ3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ4';
PHY_SIGNAL = 'DDR3_DQ4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ5';
PHY_SIGNAL = 'DDR3_DQ5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ6';
PHY_SIGNAL = 'DDR3_DQ6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ7';
PHY_SIGNAL = 'DDR3_DQ7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ8';
PHY_SIGNAL = 'DDR3_DQ8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQ9';
PHY_SIGNAL = 'DDR3_DQ9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS0_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS0_N';
PHY_SIGNAL = 'DDR3_DQS0_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS0_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS0_P';
PHY_SIGNAL = 'DDR3_DQS0_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS1_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS1_N';
PHY_SIGNAL = 'DDR3_DQS1_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS1_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_DQS1_P';
PHY_SIGNAL = 'DDR3_DQS1_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_ODT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_ODT';
PHY_SIGNAL = 'DDR3_ODT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_RAS#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_RAS#';
PHY_SIGNAL = 'DDR3_RAS#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_RST#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_RST#';
PHY_SIGNAL = 'DDR3_RST#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_WE#';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_WE#';
PHY_SIGNAL = 'DDR3_WE#';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTTVREF';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTTVREF';
PHY_SIGNAL = 'VTTVREF';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AD9963_CSN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AD9963_CSN';
PHY_SIGNAL = 'AD9963_CSN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AD9963_RESETN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AD9963_RESETN';
PHY_SIGNAL = 'AD9963_RESETN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADF4360_CS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADF4360_CS';
PHY_SIGNAL = 'ADF4360_CS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADF4360_LD';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADF4360_LD';
PHY_SIGNAL = 'ADF4360_LD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_0';
PHY_SIGNAL = 'DIO_0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_1';
PHY_SIGNAL = 'DIO_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_10';
PHY_SIGNAL = 'DIO_10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_11';
PHY_SIGNAL = 'DIO_11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_12';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_12';
PHY_SIGNAL = 'DIO_12';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_13';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_13';
PHY_SIGNAL = 'DIO_13';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_14';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_14';
PHY_SIGNAL = 'DIO_14';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_15';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_15';
PHY_SIGNAL = 'DIO_15';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_2';
PHY_SIGNAL = 'DIO_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_3';
PHY_SIGNAL = 'DIO_3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_4';
PHY_SIGNAL = 'DIO_4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_5';
PHY_SIGNAL = 'DIO_5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_6';
PHY_SIGNAL = 'DIO_6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_7';
PHY_SIGNAL = 'DIO_7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_8';
PHY_SIGNAL = 'DIO_8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DIO_9';
PHY_SIGNAL = 'DIO_9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_AWG1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_AWG1';
PHY_SIGNAL = 'EN_AWG1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_AWG2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_AWG2';
PHY_SIGNAL = 'EN_AWG2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_CAL2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_CAL2';
PHY_SIGNAL = 'EN_SC1_CAL2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_HG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_HG';
PHY_SIGNAL = 'EN_SC1_HG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_LG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC1_LG';
PHY_SIGNAL = 'EN_SC1_LG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_CAL2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_CAL2';
PHY_SIGNAL = 'EN_SC2_CAL2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_HG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_HG';
PHY_SIGNAL = 'EN_SC2_HG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_LG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC2_LG';
PHY_SIGNAL = 'EN_SC2_LG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC_CAL1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC_CAL1';
PHY_SIGNAL = 'EN_SC_CAL1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RX_CLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RX_CLK';
PHY_SIGNAL = 'RX_CLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_0';
PHY_SIGNAL = 'RXD_0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_1';
PHY_SIGNAL = 'RXD_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_10';
PHY_SIGNAL = 'RXD_10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_11';
PHY_SIGNAL = 'RXD_11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_2';
PHY_SIGNAL = 'RXD_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_3';
PHY_SIGNAL = 'RXD_3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_4';
PHY_SIGNAL = 'RXD_4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_5';
PHY_SIGNAL = 'RXD_5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_6';
PHY_SIGNAL = 'RXD_6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_7';
PHY_SIGNAL = 'RXD_7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_8';
PHY_SIGNAL = 'RXD_8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXD_9';
PHY_SIGNAL = 'RXD_9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXIQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXIQ';
PHY_SIGNAL = 'RXIQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_CAL_MUX0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_CAL_MUX0';
PHY_SIGNAL = 'SC_CAL_MUX0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_CAL_MUX1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_CAL_MUX1';
PHY_SIGNAL = 'SC_CAL_MUX1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SCLK';
PHY_SIGNAL = 'SCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SDIO';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SDIO';
PHY_SIGNAL = 'SDIO';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TRIG_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TRIG_1';
PHY_SIGNAL = 'TRIG_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TRIG_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TRIG_2';
PHY_SIGNAL = 'TRIG_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TX_CLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TX_CLK';
PHY_SIGNAL = 'TX_CLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_0';
PHY_SIGNAL = 'TXD_0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_1';
PHY_SIGNAL = 'TXD_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_10';
PHY_SIGNAL = 'TXD_10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_11';
PHY_SIGNAL = 'TXD_11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_2';
PHY_SIGNAL = 'TXD_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_3';
PHY_SIGNAL = 'TXD_3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_4';
PHY_SIGNAL = 'TXD_4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_5';
PHY_SIGNAL = 'TXD_5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_6';
PHY_SIGNAL = 'TXD_6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_7';
PHY_SIGNAL = 'TXD_7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_8';
PHY_SIGNAL = 'TXD_8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXD_9';
PHY_SIGNAL = 'TXD_9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXIQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):TXIQ';
PHY_SIGNAL = 'TXIQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC1_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC1_N';
PHY_SIGNAL = 'IN_SC1_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC1_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC1_P';
PHY_SIGNAL = 'IN_SC1_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC2_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC2_N';
PHY_SIGNAL = 'IN_SC2_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC2_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):IN_SC2_P';
PHY_SIGNAL = 'IN_SC2_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG1';
PHY_SIGNAL = 'OUT_AWG1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG2';
PHY_SIGNAL = 'OUT_AWG2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_NEG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_NEG';
PHY_SIGNAL = 'SUPPLY_NEG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_POS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_POS';
PHY_SIGNAL = 'SUPPLY_POS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_A_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_A_1';
PHY_SIGNAL = '1V8_A_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_A_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_A_2';
PHY_SIGNAL = '1V8_A_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_A';
PHY_SIGNAL = '3V3_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_A_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_A_1';
PHY_SIGNAL = '3V3_A_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC1_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC1_N';
PHY_SIGNAL = 'ADC_SC1_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC1_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC1_P';
PHY_SIGNAL = 'ADC_SC1_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC2_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC2_N';
PHY_SIGNAL = 'ADC_SC2_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC2_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADC_SC2_P';
PHY_SIGNAL = 'ADC_SC2_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG1_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG1_N';
PHY_SIGNAL = 'DAC_AVG1_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG1_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG1_P';
PHY_SIGNAL = 'DAC_AVG1_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG2_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG2_N';
PHY_SIGNAL = 'DAC_AVG2_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG2_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_AVG2_P';
PHY_SIGNAL = 'DAC_AVG2_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_NEG_9963';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_NEG_9963';
PHY_SIGNAL = 'DAC_USR_POW_NEG_9963';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_POS_9963';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_POS_9963';
PHY_SIGNAL = 'DAC_USR_POW_POS_9963';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MASTER_CLK_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MASTER_CLK_N';
PHY_SIGNAL = 'MASTER_CLK_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MASTER_CLK_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MASTER_CLK_P';
PHY_SIGNAL = 'MASTER_CLK_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V0_AWG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V0_AWG';
PHY_SIGNAL = 'REF_1V0_AWG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXCML';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):RXCML';
PHY_SIGNAL = 'RXCML';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_NEG_MONITOR';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_NEG_MONITOR';
PHY_SIGNAL = 'SUPPLY_NEG_MONITOR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_POS_MONITOR';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SUPPLY_POS_MONITOR';
PHY_SIGNAL = 'SUPPLY_POS_MONITOR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_SC_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_SC_A';
PHY_SIGNAL = '-3V3_SC_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_SC_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_SC_A';
PHY_SIGNAL = '3V3_SC_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):CALIB_REFERENCE1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):CALIB_REFERENCE1';
PHY_SIGNAL = 'CALIB_REFERENCE1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):CALIB_REFERENCE2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):CALIB_REFERENCE2';
PHY_SIGNAL = 'CALIB_REFERENCE2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MUX_EN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):MUX_EN';
PHY_SIGNAL = 'MUX_EN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_SC1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_SC1';
PHY_SIGNAL = 'OFFSET_SC1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG1_CALIB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG1_CALIB';
PHY_SIGNAL = 'OUT_AWG1_CALIB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_SC1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_SC1';
PHY_SIGNAL = 'REF_SC1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_SC2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_SC2';
PHY_SIGNAL = 'OFFSET_SC2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG2_CALIB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OUT_AWG2_CALIB';
PHY_SIGNAL = 'OUT_AWG2_CALIB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_SC2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_SC2';
PHY_SIGNAL = 'REF_SC2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_AWG_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_AWG_A';
PHY_SIGNAL = '-3V3_AWG_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_AWG_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_AWG_A';
PHY_SIGNAL = '3V3_AWG_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AWG1_PD';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AWG1_PD';
PHY_SIGNAL = 'AWG1_PD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AWG2_PD';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):AWG2_PD';
PHY_SIGNAL = 'AWG2_PD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_AWG1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_AWG1';
PHY_SIGNAL = 'OFFSET_AWG1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_AWG2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):OFFSET_AWG2';
PHY_SIGNAL = 'OFFSET_AWG2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_AWG1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_AWG1';
PHY_SIGNAL = 'REF_AWG1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_AWG2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_AWG2';
PHY_SIGNAL = 'REF_AWG2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_OFFSET_SC1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_OFFSET_SC1';
PHY_SIGNAL = 'DAC_OFFSET_SC1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_OFFSET_SC2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_OFFSET_SC2';
PHY_SIGNAL = 'DAC_OFFSET_SC2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_NEG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_NEG';
PHY_SIGNAL = 'DAC_USR_POW_NEG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_POS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DAC_USR_POW_POS';
PHY_SIGNAL = 'DAC_USR_POW_POS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V2';
PHY_SIGNAL = 'REF_1V2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V2_SC';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):REF_1V2_SC';
PHY_SIGNAL = 'REF_1V2_SC';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):20MHZ_REFCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):20MHZ_REFCLK';
PHY_SIGNAL = '20MHZ_REFCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_CLK_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_CLK_A';
PHY_SIGNAL = '3V3_CLK_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):LOOP_FILT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):LOOP_FILT';
PHY_SIGNAL = 'LOOP_FILT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PWR_GOOD';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PWR_GOOD';
PHY_SIGNAL = 'PWR_GOOD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-3V3_A';
PHY_SIGNAL = '-3V3_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SCL';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SCL';
PHY_SIGNAL = 'SCL';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SDA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SDA';
PHY_SIGNAL = 'SDA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN';
PHY_SIGNAL = 'VIN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PWR_GD_1.35V';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PWR_GD_1.35V';
PHY_SIGNAL = 'PWR_GD_1.35V';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UART_RX';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UART_RX';
PHY_SIGNAL = 'UART_RX';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UART_TX';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UART_TX';
PHY_SIGNAL = 'UART_TX';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V35';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V35';
PHY_SIGNAL = '1V35';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A14';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DDR3_A14';
PHY_SIGNAL = 'DDR3_A14';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTT_0P75';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTT_0P75';
PHY_SIGNAL = 'VTT_0P75';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TCK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TCK';
PHY_SIGNAL = 'JTAG_TCK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TDI';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TDI';
PHY_SIGNAL = 'JTAG_TDI';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TDO';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TDO';
PHY_SIGNAL = 'JTAG_TDO';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TMS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):JTAG_TMS';
PHY_SIGNAL = 'JTAG_TMS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VCCPINT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VCCPINT';
PHY_SIGNAL = 'VCCPINT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VCCPLL';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VCCPLL';
PHY_SIGNAL = 'VCCPLL';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1.35V';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1.35V';
PHY_SIGNAL = '1.35V';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1P35V';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1P35V';
PHY_SIGNAL = 'COMP_1P35V';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PG_1P0V';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PG_1P0V';
PHY_SIGNAL = 'PG_1P0V';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PG_1P8V';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PG_1P8V';
PHY_SIGNAL = 'PG_1P8V';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN_5V_USB_DATA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN_5V_USB_DATA';
PHY_SIGNAL = 'VIN_5V_USB_DATA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN_5V_USB_POWER';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VIN_5V_USB_POWER';
PHY_SIGNAL = 'VIN_5V_USB_POWER';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_CPEN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USB_OTG_CPEN';
PHY_SIGNAL = 'USB_OTG_CPEN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_D_LA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_D_LA';
PHY_SIGNAL = '3V3_D_LA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):5V0_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):5V0_A';
PHY_SIGNAL = '5V0_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_A';
PHY_SIGNAL = '-6V0_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_AWG_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_AWG_A';
PHY_SIGNAL = '-6V0_AWG_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_SC_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_SC_A';
PHY_SIGNAL = '-6V0_SC_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_USR_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-6V0_USR_A';
PHY_SIGNAL = '-6V0_USR_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V0_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V0_D';
PHY_SIGNAL = '1V0_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADP2114_VIN_1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADP2114_VIN_1';
PHY_SIGNAL = 'ADP2114_VIN_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADP2114_VIN_2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ADP2114_VIN_2';
PHY_SIGNAL = 'ADP2114_VIN_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1V0_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1V0_D';
PHY_SIGNAL = 'COMP_1V0_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_3V3_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_3V3_D';
PHY_SIGNAL = 'COMP_3V3_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V0_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V0_D';
PHY_SIGNAL = 'FB_1V0_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_3V3_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_3V3_D';
PHY_SIGNAL = 'FB_3V3_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_A';
PHY_SIGNAL = '6V0_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_SC_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_SC_A';
PHY_SIGNAL = '6V0_SC_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_USR_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_USR_A';
PHY_SIGNAL = '6V0_USR_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_AWG_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):6V0_AWG_A';
PHY_SIGNAL = '6V0_AWG_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V35';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V35';
PHY_SIGNAL = 'FB_1V35';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):FB_1V8';
PHY_SIGNAL = 'FB_1V8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1V8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):COMP_1V8';
PHY_SIGNAL = 'COMP_1V8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USR_BTN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USR_BTN';
PHY_SIGNAL = 'USR_BTN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USR_LED';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):USR_LED';
PHY_SIGNAL = 'USR_LED';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTUNE';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):VTUNE';
PHY_SIGNAL = 'VTUNE';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):4V0_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):4V0_A';
PHY_SIGNAL = '4V0_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_PD';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):SC_PD';
PHY_SIGNAL = 'SC_PD';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_SC';
PHY_SIGNAL = 'EN_SC';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_DAT_USB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_DAT_USB';
PHY_SIGNAL = 'EN_DAT_USB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_POW_USB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_POW_USB';
PHY_SIGNAL = 'EN_POW_USB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):STAT_DATA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):STAT_DATA';
PHY_SIGNAL = 'STAT_DATA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):STAT_POWER';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):STAT_POWER';
PHY_SIGNAL = 'STAT_POWER';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DONE_LED_OVERRIDE';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):DONE_LED_OVERRIDE';
PHY_SIGNAL = 'DONE_LED_OVERRIDE';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_USR_POW_NEG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_USR_POW_NEG';
PHY_SIGNAL = 'EN_USR_POW_NEG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_USR_POW_POS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):EN_USR_POW_POS';
PHY_SIGNAL = 'EN_USR_POW_POS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ENABLE_POW_NEG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ENABLE_POW_NEG';
PHY_SIGNAL = 'ENABLE_POW_NEG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ENABLE_POW_POS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):ENABLE_POW_POS';
PHY_SIGNAL = 'ENABLE_POW_POS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-5V0_SC_A';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):-5V0_SC_A';
PHY_SIGNAL = '-5V0_SC_A';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = 'NC';
LOG_SIGNAL = 'NC';
PHY_SIGNAL = 'NC';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '29';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I2@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I3@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I4@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I5@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I6@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I7@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I8@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I9@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I10@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I11@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I12@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I15@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I16@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I17@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I18@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I19@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I20@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I21@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I22@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT18';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I23@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT17';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I24@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I25@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I26@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT15';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I27@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I28@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT11';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I29@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I30@RESISTORS.RESTHERM(CHIPS)';
LOCATION   = 'RT10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/restherm/chips/chips.prt';
 PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 LONG_PART_NAME = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35-R0603H35';
 PARENT_PPT_PHYS_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_PPT = 'RESTHERM';
 PARENT_PPT_PART = 'RESTHERM_SM-220,E023781,N/A,N/A,R0603H35';
 PARENT_CHIPS_PHYS_PART = 'RESTHERM_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I31@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D11';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I32@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I33@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I34@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I35@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D15';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I36@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I37@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D17';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I38@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D18';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I39@DIODES.DIO3P_V3(CHIPS)';
LOCATION   = 'D19';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
 PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 LONG_PART_NAME = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89-SC89';
 PARENT_PPT_PHYS_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_PPT = 'DIO3P_V3';
 PARENT_PPT_PART = 'DIO3P_V3_SM-DB3S406F0L,40V,N/A,E023784,SC89';
 PARENT_CHIPS_PHYS_PART = 'DIO3P_V3_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I44@CONN_PCB.CN30P_ODD_EVEN_V2(CHIPS)';
LOCATION   = 'P1';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn30p_odd_even_v2/chips/chips.prt';
 PART_NAME = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224-CNHDRRA2X15H224';
 LONG_PART_NAME = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224-CNHDRRA2X15H224';
 PARENT_PPT_PHYS_PART = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224';
 PARENT_PPT = 'CN30P_ODD_EVEN_V2';
 PARENT_PPT_PART = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224';
 PARENT_CHIPS_PHYS_PART = 'CN30P_ODD_EVEN_V2_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I45@CONN_PCB.CN30P_ODD_EVEN_V2(CHIPS)';
LOCATION   = 'P1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn30p_odd_even_v2/chips/chips.prt';
 PART_NAME = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224-CNHDRRA2X15H224';
 LONG_PART_NAME = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224-CNHDRRA2X15H224';
 PARENT_PPT_PHYS_PART = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224';
 PARENT_PPT = 'CN30P_ODD_EVEN_V2';
 PARENT_PPT_PART = 'CN30P_ODD_EVEN_V2_TH-TSW-115-08-F-D-RA,E021381,CNHDRRA2X15H224';
 PARENT_CHIPS_PHYS_PART = 'CN30P_ODD_EVEN_V2_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I52@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TP7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I54@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TP6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE29_I56@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TP5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N10';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N11';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N12';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N12';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N13';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N13';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N14';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N14';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N15';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N15';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N7';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N8';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I44_N9';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I44_2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N10';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N11';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N12';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N12';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N13';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N13';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N14';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N14';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N15';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N15';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N7';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N8';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_29_CN30PODDEVENV2_I45_N9';
PHY_SIGNAL = 'UNNAMED_29_CN30PODDEVENV2_I45_2';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '30';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I47@IC_ADI.AD9963(CHIPS)';
LOCATION   = 'U2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad9963/chips/chips.prt';
 PART_NAME = 'AD9963_SM-AD9963BCPZ,E023805,QFN72_10X10_PAD7_1X7_1-QFN72_10X10_PAD7_1X7_1';
 LONG_PART_NAME = 'AD9963_SM-AD9963BCPZ,E023805,QFN72_10X10_PAD7_1X7_1-QFN72_10X10_PAD7_1X7_1';
 PARENT_PPT_PHYS_PART = 'AD9963_SM-AD9963BCPZ,E023805,QFN72_10X10_PAD7_1X7_1';
 PARENT_PPT = 'AD9963';
 PARENT_PPT_PART = 'AD9963_SM-AD9963BCPZ,E023805,QFN72_10X10_PAD7_1X7_1';
 PARENT_CHIPS_PHYS_PART = 'AD9963_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I49@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I50@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I54@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C48';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I55@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C43';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I56@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C38';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I74@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C61';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I75@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C57';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I76@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C53';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I78@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C33';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I79@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C28';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I80@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C58';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I82@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C54';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I83@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C50';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I84@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C45';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I85@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C39';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I86@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C34';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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BEGIN_PRIM:
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 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I172@RESISTORS.RES(CHIPS)';
LOCATION   = 'R187';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I173@RESISTORS.RES(CHIPS)';
LOCATION   = 'R188';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I174@RESISTORS.RES(CHIPS)';
LOCATION   = 'R176';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I175@RESISTORS.RES(CHIPS)';
LOCATION   = 'R175';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I176@RESISTORS.RES(CHIPS)';
LOCATION   = 'R174';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-22,E024499,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22,E024499,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I198@RESISTORS.RES(CHIPS)';
LOCATION   = 'R76';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I199@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I202@RESISTORS.RES(CHIPS)';
LOCATION   = 'R4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE30_I203@RESISTORS.RES(CHIPS)';
LOCATION   = 'R3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):1V8_D';
PHY_SIGNAL = '1V8_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):3V3_D';
PHY_SIGNAL = '3V3_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_AUXADCREF';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_AUXADCREF';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_AUXADCREF';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_DLLFILT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_DLLFILT';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_DLLFILT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_RXBIAS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_RXBIAS';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_RXBIAS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXCLK';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD0';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD1';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD10';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD11';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD2';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD3';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD4';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD5';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD6';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD7';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD8';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXD9';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXD9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXIQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TRXIQ';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TRXIQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXCLK';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXCLK';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD0';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD1';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD10';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD10';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD10';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD11';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD11';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD11';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD2';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD3';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD4';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD5';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD6';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD7';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD7';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD8';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD8';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD9';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXD9';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXD9';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXIQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_TXIQ';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_TXIQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_CAP_I112_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_CAP_I112_N1';
PHY_SIGNAL = 'UNNAMED_30_CAP_I112_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_AUXIN1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_30_AD9963_I47_AUXIN1';
PHY_SIGNAL = 'UNNAMED_30_AD9963_I47_AUXIN1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '31';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I1@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A4';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I2@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A4';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I5@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A4';
SEC = '5';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

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PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I6@IC_ADI.AD8066(CHIPS)';
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8066/chips/chips.prt';
 PART_NAME = 'AD8066_SM-AD8066ARZ,E004991,SO8-SO8';
 LONG_PART_NAME = 'AD8066_SM-AD8066ARZ,E004991,SO8-SO8';
 PARENT_PPT_PHYS_PART = 'AD8066_SM-AD8066ARZ,E004991,SO8';
 PARENT_PPT = 'AD8066';
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 PARENT_CHIPS_PHYS_PART = 'AD8066_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'C74';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.001UF,50V,2,E022455,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.001UF,50V,2,E022455,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'R18';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-21K,E021794,1/10W,1,R0603-R0603,R0603L';
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 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-21K,E021794,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-200K,E015343,1/10W,1,R0603-R0603,R0603L';
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 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-820K,E005793,1/8W,1,R0805-R0805';
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 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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BEGIN_PRIM:
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-820K,E005793,1/8W,1,R0805-R0805';
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 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
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 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
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SEC = '4';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
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 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
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 PARENT_PPT_PHYS_PART = 'RES_SM-200K,E015343,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-200K,E015343,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
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 PARENT_PPT_PHYS_PART = 'RES_SM-21K,E021794,1/10W,1,R0603';
 PARENT_PPT = 'RES';
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.001UF,50V,2,E022455,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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BEGIN_PRIM:
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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LOCATION   = 'A3';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8066/chips/chips.prt';
 PART_NAME = 'AD8066_SM-AD8066ARZ,E004991,SO8-SO8';
 LONG_PART_NAME = 'AD8066_SM-AD8066ARZ,E004991,SO8-SO8';
 PARENT_PPT_PHYS_PART = 'AD8066_SM-AD8066ARZ,E004991,SO8';
 PARENT_PPT = 'AD8066';
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 PARENT_CHIPS_PHYS_PART = 'AD8066_SM';
END_LIB_INFO;
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LOCATION   = 'R23';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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LOCATION   = 'C88';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I191@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C335';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I192@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C333';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I194@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C76';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I195@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C73';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I196@RESISTORS.RES(CHIPS)';
LOCATION   = 'R30';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I197@RESISTORS.RES(CHIPS)';
LOCATION   = 'R31';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I198@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C75';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I199@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C72';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I200@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C122';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10PF,50V,5,E007982,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-10PF,50V,5,E007982,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10PF,50V,5,E007982,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10PF,50V,5,E007982,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I201@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A2';
SEC = '5';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I202@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A2';
SEC = '4';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I203@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I204@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C103';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I205@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C104';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I232@IC_ADI.ADA4940_2_V2(CHIPS)';
LOCATION   = 'U3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I233@IC_ADI.ADA4940_2_V2(CHIPS)';
LOCATION   = 'U3';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I234@IC_ADI.ADA4940_2_V2(CHIPS)';
LOCATION   = 'U3';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I235@IC_ADI.ADG1404_V2(CHIPS)';
LOCATION   = 'U8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg1404_v2/chips/chips.prt';
 PART_NAME = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5-QFN16_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5-QFN16_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADG1404_V2';
 PARENT_PPT_PART = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADG1404_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I236@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C189';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I237@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C336';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I238@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C181';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE31_I239@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C185';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_INV';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I55_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_NINV';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I55_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I55_OUT';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I55_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_INV';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I6_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_NINV';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I6_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_AD8066_I6_OUT';
PHY_SIGNAL = 'UNNAMED_31_AD8066_I6_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I19_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I19_D';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I19_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I19_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I19_S';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I19_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I1_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I1_D';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I1_D';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I1_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I1_S';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I1_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I20_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I20_S';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I20_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I2_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG202N_I2_S';
PHY_SIGNAL = 'UNNAMED_31_ADG202N_I2_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_DIO3PV3_I80_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_DIO3PV3_I80_N';
PHY_SIGNAL = 'UNNAMED_31_DIO3PV3_I80_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_DIO3PV3_I80_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_DIO3PV3_I80_P';
PHY_SIGNAL = 'UNNAMED_31_DIO3PV3_I80_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232_';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__1';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232__1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__2';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232__2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__3';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232__3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__4';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232__4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232__5';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232__5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232_VOCM';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I232_VOCM';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I232_VOCM';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233_';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__1';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233__1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__2';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233__2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__3';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233__3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__4';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233__4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADA49402V2_I233__5';
PHY_SIGNAL = 'UNNAMED_31_ADA49402V2_I233__5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG1404V2_I235_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_31_ADG1404V2_I235_D';
PHY_SIGNAL = 'UNNAMED_31_ADG1404V2_I235_D';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '32';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I2@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C124';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I4@CAPACITORS.CAPVAR(CHIPS)';
LOCATION   = 'C128';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/capvar/chips/chips.prt';
 PART_NAME = 'CAPVAR_SM-5-20PF,100V,N/A,E023860,CSML177W126H67-CSML177W126H67';
 LONG_PART_NAME = 'CAPVAR_SM-5-20PF,100V,N/A,E023860,CSML177W126H67-CSML177W126H67';
 PARENT_PPT_PHYS_PART = 'CAPVAR_SM-5-20PF,100V,N/A,E023860,CSML177W126H67';
 PARENT_PPT = 'CAPVAR';
 PARENT_PPT_PART = 'CAPVAR_SM-5-20PF,100V,N/A,E023860,CSML177W126H67';
 PARENT_CHIPS_PHYS_PART = 'CAPVAR_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I6@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C125';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I7@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C127';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I9@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A1';
SEC = '5';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C135';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I11@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C136';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I13@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C137';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I15@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C148';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I16@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C151';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I17@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C153';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I18@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A1';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I19@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C134';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.001UF,50V,2,E022455,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.001UF,50V,2,E022455,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.001UF,50V,2,E022455,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I21@RESISTORS.RES(CHIPS)';
LOCATION   = 'R46';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-21K,E021794,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-21K,E021794,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-21K,E021794,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-21K,E021794,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I22@RESISTORS.RES(CHIPS)';
LOCATION   = 'R45';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-200K,E015343,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-200K,E015343,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-200K,E015343,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-200K,E015343,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I24@RESISTORS.RES(CHIPS)';
LOCATION   = 'R44';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-820K,E005793,1/8W,1,R0805-R0805';
 LONG_PART_NAME = 'RES_SM-820K,E005793,1/8W,1,R0805-R0805';
 PARENT_PPT_PHYS_PART = 'RES_SM-820K,E005793,1/8W,1,R0805';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-820K,E005793,1/8W,1,R0805';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I25@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A1';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG612YRUZ,E006320,TSSOP16-TSSOP16';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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END_LIB_INFO;
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BEGIN_LIB_INFO:
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END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio3p_v3/chips/chips.prt';
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I144@RESISTORS.RES(CHIPS)';
LOCATION   = 'R54';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I145@RESISTORS.RES(CHIPS)';
LOCATION   = 'R55';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3.9K,E014697,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3.9K,E014697,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I146@RESISTORS.RES(CHIPS)';
LOCATION   = 'R52';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3K,E022429,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3K,E022429,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3K,E022429,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3K,E022429,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I147@RESISTORS.RES(CHIPS)';
LOCATION   = 'R53';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3K,E022429,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3K,E022429,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3K,E022429,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3K,E022429,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I148@RESISTORS.RES(CHIPS)';
LOCATION   = 'R51';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I149@RESISTORS.RES(CHIPS)';
LOCATION   = 'R50';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I150@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C146';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-150PF,50V,5,E012646,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-150PF,50V,5,E012646,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-150PF,50V,5,E012646,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-150PF,50V,5,E012646,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I151@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C147';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-150PF,50V,5,E012646,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-150PF,50V,5,E012646,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-150PF,50V,5,E012646,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-150PF,50V,5,E012646,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I156@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C95';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I157@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C130';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-82PF,50V,5,E000414,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-82PF,50V,5,E000414,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I158@RESISTORS.RES(CHIPS)';
LOCATION   = 'R57';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I159@RESISTORS.RES(CHIPS)';
LOCATION   = 'R56';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11.3K,E019952,1/16W,0.1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I160@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C129';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I161@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C132';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I162@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C173';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10PF,50V,5,E007982,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-10PF,50V,5,E007982,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10PF,50V,5,E007982,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10PF,50V,5,E007982,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I163@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A2';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I164@IC_ADI.ADG202N(CHIPS)';
LOCATION   = 'A2';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg202n/chips/chips.prt';
 PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 LONG_PART_NAME = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16-TSSOP16';
 PARENT_PPT_PHYS_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_PPT = 'ADG202N';
 PARENT_PPT_PART = 'ADG202N_SM-ADG611YRUZ,E022133,TSSOP16';
 PARENT_CHIPS_PHYS_PART = 'ADG202N_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I165@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C162';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I166@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C163';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'U4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I191@IC_ADI.ADA4940_2_V2(CHIPS)';
LOCATION   = 'U4';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I192@IC_ADI.ADA4940_2_V2(CHIPS)';
LOCATION   = 'U4';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ada4940_2_v2/chips/chips.prt';
 PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5-QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADA4940_2_V2';
 PARENT_PPT_PART = 'ADA4940_2_V2_SM-ADA4940-2ACPZ,E017451,QFN24_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADA4940_2_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I201@IC_ADI.ADG1404_V2(CHIPS)';
LOCATION   = 'U9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adg1404_v2/chips/chips.prt';
 PART_NAME = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5-QFN16_4X4_PAD2_5X2_5';
 LONG_PART_NAME = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5-QFN16_4X4_PAD2_5X2_5';
 PARENT_PPT_PHYS_PART = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5';
 PARENT_PPT = 'ADG1404_V2';
 PARENT_PPT_PART = 'ADG1404_V2_SM-ADG1404YCPZ,E029836,QFN16_4X4_PAD2_5X2_5';
 PARENT_CHIPS_PHYS_PART = 'ADG1404_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I202@TRANSISTORS.TRANIRLMLXXXX(CHIPS)';
LOCATION   = 'Q3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/tranirlmlxxxx/chips/chips.prt';
 PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 LONG_PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 PARENT_PPT_PHYS_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_PPT = 'TRANIRLMLXXXX';
 PARENT_PPT_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_CHIPS_PHYS_PART = 'TRANIRLMLXXXX_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I203@RESISTORS.RES(CHIPS)';
LOCATION   = 'R131';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I205@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C337';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I206@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C338';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I207@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C339';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3PF,50V,0.05PF,E033791,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE32_I208@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C340';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,50V,0.25PF,E000276,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_INV';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I42_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_NINV';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I42_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I42_OUT';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I42_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_INV';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I82_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_NINV';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I82_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_AD8066_I82_OUT';
PHY_SIGNAL = 'UNNAMED_32_AD8066_I82_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I163_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I163_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I163_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I164_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I164_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I164_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I18_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I18_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I18_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I25_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I25_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I25_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I26_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I26_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I26_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I34_S';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG202N_I34_S';
PHY_SIGNAL = 'UNNAMED_32_ADG202N_I34_S';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_DIO3PV3_I76_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_DIO3PV3_I76_N';
PHY_SIGNAL = 'UNNAMED_32_DIO3PV3_I76_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_DIO3PV3_I76_P';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_DIO3PV3_I76_P';
PHY_SIGNAL = 'UNNAMED_32_DIO3PV3_I76_P';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190_';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__1';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190__1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__2';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190__2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__3';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190__3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__4';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190__4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190__5';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190__5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190_VOCM';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I190_VOCM';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I190_VOCM';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191_';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__1';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191__1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__2';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191__2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__3';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191__3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__4';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__4';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191__4';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADA49402V2_I191__5';
PHY_SIGNAL = 'UNNAMED_32_ADA49402V2_I191__5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG1404V2_I201_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_32_ADG1404V2_I201_D';
PHY_SIGNAL = 'UNNAMED_32_ADG1404V2_I201_D';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '33';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I1@IC_ADI.ADOPAMP2(CHIPS)';
LOCATION   = 'A10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adopamp2/chips/chips.prt';
 PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 LONG_PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 PARENT_PPT_PHYS_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_PPT = 'ADOPAMP2';
 PARENT_PPT_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_CHIPS_PHYS_PART = 'ADOPAMP2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I2@IC_ADI.ADOPAMP2(CHIPS)';
LOCATION   = 'A10';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adopamp2/chips/chips.prt';
 PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 LONG_PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 PARENT_PPT_PHYS_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_PPT = 'ADOPAMP2';
 PARENT_PPT_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_CHIPS_PHYS_PART = 'ADOPAMP2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I3@RESISTORS.RES(CHIPS)';
LOCATION   = 'R95';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I5@RESISTORS.RES(CHIPS)';
LOCATION   = 'R93';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I9@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C243';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C242';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I11@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C245';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I12@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C247';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I13@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C244';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
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BEGIN_LIB_INFO:
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 PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I101@IC_ADI.ADOPAMP2(CHIPS)';
LOCATION   = 'A10';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adopamp2/chips/chips.prt';
 PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 LONG_PART_NAME = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8-SO8';
 PARENT_PPT_PHYS_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_PPT = 'ADOPAMP2';
 PARENT_PPT_PART = 'ADOPAMP2_SM-AD8058ARZ,E013610,SO8';
 PARENT_CHIPS_PHYS_PART = 'ADOPAMP2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I102@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C261';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I103@RESISTORS.RES(CHIPS)';
LOCATION   = 'R106';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1.47K,E007637,0.1W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-1.47K,E007637,0.1W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-1.47K,E007637,0.1W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1.47K,E007637,0.1W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I108@RESISTORS.RES(CHIPS)';
LOCATION   = 'R94';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-124,E004853,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-124,E004853,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I123@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C267';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I124@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C266';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1PF,25V,0.1PF,E011093,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I133@RESISTORS.RES(CHIPS)';
LOCATION   = 'R97';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I134@RESISTORS.RES(CHIPS)';
LOCATION   = 'R98';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I135@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C248';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I136@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C249';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I137@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C252';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I138@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C255';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-3.9PF,50V,0.1PF,E014597,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I139@IC_ADI.AD8000(CHIPS)';
LOCATION   = 'A7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8000/chips/chips.prt';
 PART_NAME = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45-QFN8_3X3_PAD1_75X1_45';
 LONG_PART_NAME = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45-QFN8_3X3_PAD1_75X1_45';
 PARENT_PPT_PHYS_PART = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45';
 PARENT_PPT = 'AD8000';
 PARENT_PPT_PART = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45';
 PARENT_CHIPS_PHYS_PART = 'AD8000_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I141@IC_ADI.AD8000(CHIPS)';
LOCATION   = 'A9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8000/chips/chips.prt';
 PART_NAME = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45-QFN8_3X3_PAD1_75X1_45';
 LONG_PART_NAME = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45-QFN8_3X3_PAD1_75X1_45';
 PARENT_PPT_PHYS_PART = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45';
 PARENT_PPT = 'AD8000';
 PARENT_PPT_PART = 'AD8000_SM-AD8000YCPZ,E006723,QFN8_3X3_PAD1_75X1_45';
 PARENT_CHIPS_PHYS_PART = 'AD8000_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I143@RESISTORS.RES(CHIPS)';
LOCATION   = 'R194';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11K,E015614,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11K,E015614,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11K,E015614,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11K,E015614,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I151@TRANSISTORS.TRANNMOSFET_V8(CHIPS)';
LOCATION   = 'Q8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/trannmosfet_v8/chips/chips.prt';
 PART_NAME = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23-SOT23';
 LONG_PART_NAME = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23-SOT23';
 PARENT_PPT_PHYS_PART = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23';
 PARENT_PPT = 'TRANNMOSFET_V8';
 PARENT_PPT_PART = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23';
 PARENT_CHIPS_PHYS_PART = 'TRANNMOSFET_V8_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I153@TRANSISTORS.TRANNMOSFET_V8(CHIPS)';
LOCATION   = 'Q9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/trannmosfet_v8/chips/chips.prt';
 PART_NAME = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23-SOT23';
 LONG_PART_NAME = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23-SOT23';
 PARENT_PPT_PHYS_PART = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23';
 PARENT_PPT = 'TRANNMOSFET_V8';
 PARENT_PPT_PART = 'TRANNMOSFET_V8_SM-BSS123LT1G,E022331,SOT23';
 PARENT_CHIPS_PHYS_PART = 'TRANNMOSFET_V8_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I156@RESISTORS.RES(CHIPS)';
LOCATION   = 'R201';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I157@RESISTORS.RES(CHIPS)';
LOCATION   = 'R202';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I158@RESISTORS.RES(CHIPS)';
LOCATION   = 'R193';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-11K,E015614,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-11K,E015614,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-11K,E015614,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-11K,E015614,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I160@RESISTORS.RES(CHIPS)';
LOCATION   = 'R101';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I161@RESISTORS.RES(CHIPS)';
LOCATION   = 'R107';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-2.21K,E003783,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-2.21K,E003783,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-2.21K,E003783,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-2.21K,E003783,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I162@RESISTORS.RES(CHIPS)';
LOCATION   = 'R108';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-2.21K,E003783,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-2.21K,E003783,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-2.21K,E003783,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-2.21K,E003783,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I164@RESISTORS.RES(CHIPS)';
LOCATION   = 'R103';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I185@RESISTORS.RES(CHIPS)';
LOCATION   = 'R134';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I186@RESISTORS.RES(CHIPS)';
LOCATION   = 'R198';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I187@RESISTORS.RES(CHIPS)';
LOCATION   = 'R135';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I188@RESISTORS.RES(CHIPS)';
LOCATION   = 'R197';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I199@RESISTORS.RES(CHIPS)';
LOCATION   = 'R133';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-49.9,E003114,1/4W,1,R1206-R1206';
 LONG_PART_NAME = 'RES_SM-49.9,E003114,1/4W,1,R1206-R1206';
 PARENT_PPT_PHYS_PART = 'RES_SM-49.9,E003114,1/4W,1,R1206';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-49.9,E003114,1/4W,1,R1206';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I200@RESISTORS.RES(CHIPS)';
LOCATION   = 'R132';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-49.9,E003114,1/4W,1,R1206-R1206';
 LONG_PART_NAME = 'RES_SM-49.9,E003114,1/4W,1,R1206-R1206';
 PARENT_PPT_PHYS_PART = 'RES_SM-49.9,E003114,1/4W,1,R1206';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-49.9,E003114,1/4W,1,R1206';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I202@RESISTORS.RES(CHIPS)';
LOCATION   = 'R104';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100,E016329,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-100,E016329,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-100,E016329,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-100,E016329,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I203@RESISTORS.RES(CHIPS)';
LOCATION   = 'R102';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100,E016329,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-100,E016329,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-100,E016329,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-100,E016329,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I205@RESISTORS.RES(CHIPS)';
LOCATION   = 'R100';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3K,E013586,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-3K,E013586,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-3K,E013586,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3K,E013586,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I206@RESISTORS.RES(CHIPS)';
LOCATION   = 'R99';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3K,E013586,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-3K,E013586,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-3K,E013586,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-3K,E013586,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I207@RESISTORS.RES(CHIPS)';
LOCATION   = 'R200';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE33_I208@RESISTORS.RES(CHIPS)';
LOCATION   = 'R199';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_FB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_FB';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I139_FB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_INV';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I139_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_NINV';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I139_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I139_OUT';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I139_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_FB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_FB';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I141_FB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_INV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_INV';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I141_INV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_NINV';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_NINV';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I141_NINV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_AD8000_I141_OUT';
PHY_SIGNAL = 'UNNAMED_33_AD8000_I141_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_ADOPAMP2_I101_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_ADOPAMP2_I101_OUT';
PHY_SIGNAL = 'UNNAMED_33_ADOPAMP2_I101_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_ADOPAMP2_I1_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_ADOPAMP2_I1_OUT';
PHY_SIGNAL = 'UNNAMED_33_ADOPAMP2_I1_OUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I123_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I123_N2';
PHY_SIGNAL = 'UNNAMED_33_CAP_I123_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I124_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I124_N2';
PHY_SIGNAL = 'UNNAMED_33_CAP_I124_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I33_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I33_N1';
PHY_SIGNAL = 'UNNAMED_33_CAP_I33_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I95_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_33_CAP_I95_N1';
PHY_SIGNAL = 'UNNAMED_33_CAP_I95_N1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '34';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I1@IC_ADI.ADR34XX(CHIPS)';
LOCATION   = 'U19';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adr34xx/chips/chips.prt';
 PART_NAME = 'ADR34XX_SM-ADR3412ARJZ,E015880,SOT23_6-2-SOT23_6-2';
 LONG_PART_NAME = 'ADR34XX_SM-ADR3412ARJZ,E015880,SOT23_6-2-SOT23_6-2';
 PARENT_PPT_PHYS_PART = 'ADR34XX_SM-ADR3412ARJZ,E015880,SOT23_6-2';
 PARENT_PPT = 'ADR34XX';
 PARENT_PPT_PART = 'ADR34XX_SM-ADR3412ARJZ,E015880,SOT23_6-2';
 PARENT_CHIPS_PHYS_PART = 'ADR34XX_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I9@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C287';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C285';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I11@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C291';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I12@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C293';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I82@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C290';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I83@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C288';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I116@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C295';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I119@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C294';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
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 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I251@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A13';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I252@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I253@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A8';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I254@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I255@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A6';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I256@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I257@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A13';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I284@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A11';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE34_I285@RESISTORS.RES(CHIPS)';
LOCATION   = 'R143';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100,E003760,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-100,E003760,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-100,E003760,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-100,E003760,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X5_I239_ADDR1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X5_I239_ADDR1';
PHY_SIGNAL = 'UNNAMED_34_AD56X5_I239_ADDR1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X5_I239_CLRN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X5_I239_CLRN';
PHY_SIGNAL = 'UNNAMED_34_AD56X5_I239_CLRN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_ADDR';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_ADDR';
PHY_SIGNAL = 'UNNAMED_34_AD56X7_I238_ADDR';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_CLRN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_CLRN';
PHY_SIGNAL = 'UNNAMED_34_AD56X7_I238_CLRN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_VOUTA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_VOUTA';
PHY_SIGNAL = 'UNNAMED_34_AD56X7_I238_VOUTA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_VOUTB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD56X7_I238_VOUTB';
PHY_SIGNAL = 'UNNAMED_34_AD56X7_I238_VOUTB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I252_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I252_';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I252_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I253_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I253_';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I253_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I254_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I254_';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I254_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I255_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I255_';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I255_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284_';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I284_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284__1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284__1';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I284__1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284_OUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_34_AD8657V2_I284_OUT';
PHY_SIGNAL = 'UNNAMED_34_AD8657V2_I284_OUT';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '36';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I3@RESISTORS.RES(CHIPS)';
LOCATION   = 'R85';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I5@RESISTORS.RES(CHIPS)';
LOCATION   = 'R83';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I10@RESISTORS.RES(CHIPS)';
LOCATION   = 'R84';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I18@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C230';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I20@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C227';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I23@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C226';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I24@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C228';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I25@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C229';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I26@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C231';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I27@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C232';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I28@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C233';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I29@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C234';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I30@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C235';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I31@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C236';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I32@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C237';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-100PF,50V,5,E024302,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100PF,50V,5,E024302,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I36@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C224';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I37@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C225';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I40@IC_ADI.ADF4360_9(CHIPS)';
LOCATION   = 'U14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adf4360_9/chips/chips.prt';
 PART_NAME = 'ADF4360_9_SM-ADF4360-9BCPZ,E023893,QFN24_4X4_PAD2_3X2_3-QFN24_4X4_PAD2_3X2_3';
 LONG_PART_NAME = 'ADF4360_9_SM-ADF4360-9BCPZ,E023893,QFN24_4X4_PAD2_3X2_3-QFN24_4X4_PAD2_3X2_3';
 PARENT_PPT_PHYS_PART = 'ADF4360_9_SM-ADF4360-9BCPZ,E023893,QFN24_4X4_PAD2_3X2_3';
 PARENT_PPT = 'ADF4360_9';
 PARENT_PPT_PART = 'ADF4360_9_SM-ADF4360-9BCPZ,E023893,QFN24_4X4_PAD2_3X2_3';
 PARENT_CHIPS_PHYS_PART = 'ADF4360_9_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I42@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-270NH,2,E010087,L7144-L7144';
 LONG_PART_NAME = 'IND_SM-270NH,2,E010087,L7144-L7144';
 PARENT_PPT_PHYS_PART = 'IND_SM-270NH,2,E010087,L7144';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-270NH,2,E010087,L7144';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I43@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-270NH,2,E010087,L7144-L7144';
 LONG_PART_NAME = 'IND_SM-270NH,2,E010087,L7144-L7144';
 PARENT_PPT_PHYS_PART = 'IND_SM-270NH,2,E010087,L7144';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-270NH,2,E010087,L7144';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I44@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L15';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-220NH,2,E024706,L7144-L7144';
 LONG_PART_NAME = 'IND_SM-220NH,2,E024706,L7144-L7144';
 PARENT_PPT_PHYS_PART = 'IND_SM-220NH,2,E024706,L7144';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-220NH,2,E024706,L7144';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I45@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-220NH,2,E024706,L7144-L7144';
 LONG_PART_NAME = 'IND_SM-220NH,2,E024706,L7144-L7144';
 PARENT_PPT_PHYS_PART = 'IND_SM-220NH,2,E024706,L7144';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-220NH,2,E024706,L7144';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I46@CRYSTALS.XTALOSC4P_V9(CHIPS)';
LOCATION   = 'Y1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/crystals/xtalosc4p_v9/chips/chips.prt';
 PART_NAME = 'XTALOSC4P_V9_SM-20MHZ,E024704,YSML197W126H59-2-YSML197W126H59-2';
 LONG_PART_NAME = 'XTALOSC4P_V9_SM-20MHZ,E024704,YSML197W126H59-2-YSML197W126H59-2';
 PARENT_PPT_PHYS_PART = 'XTALOSC4P_V9_SM-20MHZ,E024704,YSML197W126H59-2';
 PARENT_PPT = 'XTALOSC4P_V9';
 PARENT_PPT_PART = 'XTALOSC4P_V9_SM-20MHZ,E024704,YSML197W126H59-2';
 PARENT_CHIPS_PHYS_PART = 'XTALOSC4P_V9_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I47@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C52';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1000PF,25V,10,E025706,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1000PF,25V,10,E025706,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1000PF,25V,10,E025706,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1000PF,25V,10,E025706,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I48@RESISTORS.RES(CHIPS)';
LOCATION   = 'R86';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-22K,E018369,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-22K,E018369,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-22K,E018369,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-22K,E018369,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I49@RESISTORS.RES(CHIPS)';
LOCATION   = 'R6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I50@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C223';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-12PF,50V,1,E033792,C0402-C0402';
 LONG_PART_NAME = 'CAP_SM-12PF,50V,1,E033792,C0402-C0402';
 PARENT_PPT_PHYS_PART = 'CAP_SM-12PF,50V,1,E033792,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-12PF,50V,1,E033792,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I52@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C239';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7PF,50V,0.05PF,E021938,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7PF,50V,0.05PF,E021938,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7PF,50V,0.05PF,E021938,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7PF,50V,0.05PF,E021938,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE36_I53@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C238';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-220PF,50V,5,E018153,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-220PF,50V,5,E018153,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-220PF,50V,5,E018153,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-220PF,50V,5,E018153,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_CC';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_CC';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_CC';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_CN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_CN';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_CN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_L1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_L1';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_L1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_L2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_L2';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_L2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RFOUTA';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RFOUTA';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_RFOUTA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RFOUTB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RFOUTB';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_RFOUTB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RSET';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_ADF43609_I40_RSET';
PHY_SIGNAL = 'UNNAMED_36_ADF43609_I40_RSET';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_CAP_I47_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_CAP_I47_N1';
PHY_SIGNAL = 'UNNAMED_36_CAP_I47_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_CAP_I53_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_36_CAP_I53_N1';
PHY_SIGNAL = 'UNNAMED_36_CAP_I53_N1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '39';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I1@RESISTORS.RES(CHIPS)';
LOCATION   = 'R791';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I11@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '5';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I15@CRYSTALS.XTALOSC4P_V7(CHIPS)';
LOCATION   = 'Y523';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/crystals/xtalosc4p_v7/chips/chips.prt';
 PART_NAME = 'XTALOSC4P_V7_SM-24MEGHZ,E022374,YSML98W79H35-YSML98W79H35';
 LONG_PART_NAME = 'XTALOSC4P_V7_SM-24MEGHZ,E022374,YSML98W79H35-YSML98W79H35';
 PARENT_PPT_PHYS_PART = 'XTALOSC4P_V7_SM-24MEGHZ,E022374,YSML98W79H35';
 PARENT_PPT = 'XTALOSC4P_V7';
 PARENT_PPT_PART = 'XTALOSC4P_V7_SM-24MEGHZ,E022374,YSML98W79H35';
 PARENT_CHIPS_PHYS_PART = 'XTALOSC4P_V7_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I27@RESISTORS.RES(CHIPS)';
LOCATION   = 'R800';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I29@IC_OTHER.ICUSB3320C(CHIPS)';
LOCATION   = 'U524';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icusb3320c/chips/chips.prt';
 PART_NAME = 'ICUSB3320C_SM-USB3320C-EZK,E021334,QFN32_5X5_PAD3_3X3_3-QFN32_5X5_PAD3_3X3_3';
 LONG_PART_NAME = 'ICUSB3320C_SM-USB3320C-EZK,E021334,QFN32_5X5_PAD3_3X3_3-QFN32_5X5_PAD3_3X3_3';
 PARENT_PPT_PHYS_PART = 'ICUSB3320C_SM-USB3320C-EZK,E021334,QFN32_5X5_PAD3_3X3_3';
 PARENT_PPT = 'ICUSB3320C';
 PARENT_PPT_PART = 'ICUSB3320C_SM-USB3320C-EZK,E021334,QFN32_5X5_PAD3_3X3_3';
 PARENT_CHIPS_PHYS_PART = 'ICUSB3320C_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I30@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C789';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I31@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C790';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I40@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C792';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I49@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C795';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I66@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C801';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-2.2UF,10V,10,E017584,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-2.2UF,10V,10,E017584,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-2.2UF,10V,10,E017584,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-2.2UF,10V,10,E017584,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I67@RESISTORS.RES(CHIPS)';
LOCATION   = 'R797';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-33,E020519,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-33,E020519,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-33,E020519,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-33,E020519,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I73@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C793';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I75@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C805';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I76@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C807';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I77@RESISTORS.RES(CHIPS)';
LOCATION   = 'R798';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I78@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C788';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 LONG_PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE39_I79@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C803';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_ICUSB3320C_I29_RBIAS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_ICUSB3320C_I29_RBIAS';
PHY_SIGNAL = 'UNNAMED_39_ICUSB3320C_I29_RBIAS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_ICUSB3320C_I29_REFCLK';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_ICUSB3320C_I29_REFCLK';
PHY_SIGNAL = 'UNNAMED_39_ICUSB3320C_I29_REFCL';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_RES_I67_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_39_RES_I67_N2';
PHY_SIGNAL = 'UNNAMED_39_RES_I67_N2';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '40';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I6@CRYSTALS.XTALOSC4P_V7(CHIPS)';
LOCATION   = 'Y578';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/crystals/xtalosc4p_v7/chips/chips.prt';
 PART_NAME = 'XTALOSC4P_V7_SM-33.333MEGHZ,E024048,YSML98W79H35-YSML98W79H35';
 LONG_PART_NAME = 'XTALOSC4P_V7_SM-33.333MEGHZ,E024048,YSML98W79H35-YSML98W79H35';
 PARENT_PPT_PHYS_PART = 'XTALOSC4P_V7_SM-33.333MEGHZ,E024048,YSML98W79H35';
 PARENT_PPT = 'XTALOSC4P_V7';
 PARENT_PPT_PART = 'XTALOSC4P_V7_SM-33.333MEGHZ,E024048,YSML98W79H35';
 PARENT_CHIPS_PHYS_PART = 'XTALOSC4P_V7_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I8@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C579';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I14@RESISTORS.RES(CHIPS)';
LOCATION   = 'R583';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I15@RESISTORS.RES(CHIPS)';
LOCATION   = 'R586';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-240,E010877,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-240,E010877,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-240,E010877,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-240,E010877,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I16@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '4';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I27@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C589';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I30@RESISTORS.RES(CHIPS)';
LOCATION   = 'R590';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I31@RESISTORS.RES(CHIPS)';
LOCATION   = 'R591';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I33@RESISTORS.RES(CHIPS)';
LOCATION   = 'R593';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I35@RESISTORS.RES(CHIPS)';
LOCATION   = 'R594';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I36@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C595';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 LONG_PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I37@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C596';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I39@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C597';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I40@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C598';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I42@RESISTORS.RES(CHIPS)';
LOCATION   = 'R587';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I43@RESISTORS.RES(CHIPS)';
LOCATION   = 'R585';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I44@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C588';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I45@RESISTORS.RES(CHIPS)';
LOCATION   = 'R584';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I46@RESISTORS.RES(CHIPS)';
LOCATION   = 'R592';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I48@RESISTORS.RES(CHIPS)';
LOCATION   = 'R581';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-33,E020519,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-33,E020519,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-33,E020519,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-33,E020519,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I49@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C599';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I50@IC_OTHER.ICMT25Q(CHIPS)';
LOCATION   = 'U508';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icmt25q/chips/chips.prt';
 PART_NAME = 'ICMT25Q_SM-MT25QU256ABA8E12-1SIT,E027529,TBGA24-TBGA24';
 LONG_PART_NAME = 'ICMT25Q_SM-MT25QU256ABA8E12-1SIT,E027529,TBGA24-TBGA24';
 PARENT_PPT_PHYS_PART = 'ICMT25Q_SM-MT25QU256ABA8E12-1SIT,E027529,TBGA24';
 PARENT_PPT = 'ICMT25Q';
 PARENT_PPT_PART = 'ICMT25Q_SM-MT25QU256ABA8E12-1SIT,E027529,TBGA24';
 PARENT_CHIPS_PHYS_PART = 'ICMT25Q_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I51@SWITCHES.SWSPST5P_V2(CHIPS)';
LOCATION   = 'S1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/switches/swspst5p_v2/chips/chips.prt';
 PART_NAME = 'SWSPST5P_V2_SM-PTS840 GKP SMTR LFS,E024294,SWSML140W138H55-SWSML140W138H55';
 LONG_PART_NAME = 'SWSPST5P_V2_SM-PTS840 GKP SMTR LFS,E024294,SWSML140W138H55-SWSML140W138H55';
 PARENT_PPT_PHYS_PART = 'SWSPST5P_V2_SM-PTS840 GKP SMTR LFS,E024294,SWSML140W138H55';
 PARENT_PPT = 'SWSPST5P_V2';
 PARENT_PPT_PART = 'SWSPST5P_V2_SM-PTS840 GKP SMTR LFS,E024294,SWSML140W138H55';
 PARENT_CHIPS_PHYS_PART = 'SWSPST5P_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE40_I53@RESISTORS.RES(CHIPS)';
LOCATION   = 'R145';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSCLK500';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSCLK500';
PHY_SIGNAL = 'UNNAMED_40_ICXC7Z010_I16_PSCLK5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSMIO7500';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSMIO7500';
PHY_SIGNAL = 'UNNAMED_40_ICXC7Z010_I16_PSMIO7';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSMIO8500';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_ICXC7Z010_I16_PSMIO8500';
PHY_SIGNAL = 'UNNAMED_40_ICXC7Z010_I16_PSMIO8';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_RES_I48_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_40_RES_I48_N1';
PHY_SIGNAL = 'UNNAMED_40_RES_I48_N1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '41';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I1@RESISTORS.RES(CHIPS)';
LOCATION   = 'R606';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I2@RESISTORS.RES(CHIPS)';
LOCATION   = 'R613';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I3@RESISTORS.RES(CHIPS)';
LOCATION   = 'R605';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I4@RESISTORS.RES(CHIPS)';
LOCATION   = 'R604';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I5@RESISTORS.RES(CHIPS)';
LOCATION   = 'R603';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I6@RESISTORS.RES(CHIPS)';
LOCATION   = 'R602';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I7@RESISTORS.RES(CHIPS)';
LOCATION   = 'R612';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I8@RESISTORS.RES(CHIPS)';
LOCATION   = 'R611';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-120,E011549,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120,E011549,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I95@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C656';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I96@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C659';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I97@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C662';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE41_I99@IC_OTHER.ICMT41K256M16(CHIPS)';
LOCATION   = 'U646';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icmt41k256m16/chips/chips.prt';
 PART_NAME = 'ICMT41K256M16_SM-MT41K256M16TW-107:P,E025442,FBGA96_C-FBGA96_C';
 LONG_PART_NAME = 'ICMT41K256M16_SM-MT41K256M16TW-107:P,E025442,FBGA96_C-FBGA96_C';
 PARENT_PPT_PHYS_PART = 'ICMT41K256M16_SM-MT41K256M16TW-107:P,E025442,FBGA96_C';
 PARENT_PPT = 'ICMT41K256M16';
 PARENT_PPT_PART = 'ICMT41K256M16_SM-MT41K256M16TW-107:P,E025442,FBGA96_C';
 PARENT_CHIPS_PHYS_PART = 'ICMT41K256M16_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_CAP_I89_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_CAP_I89_N1';
PHY_SIGNAL = 'UNNAMED_41_CAP_I89_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_S3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_S3';
PHY_SIGNAL = 'UNNAMED_41_ICTPS51206_I44_S3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_S5';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_S5';
PHY_SIGNAL = 'UNNAMED_41_ICTPS51206_I44_S5';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_VLDOIN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICTPS51206_I44_VLDOIN';
PHY_SIGNAL = 'UNNAMED_41_ICTPS51206_I44_VLDOI';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICXC7Z010_I26_PSDDRVRN502';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICXC7Z010_I26_PSDDRVRN502';
PHY_SIGNAL = 'UNNAMED_41_ICXC7Z010_I26_PSDDRV';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICXC7Z010_I26_PSDDRVRP502';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICXC7Z010_I26_PSDDRVRP502';
PHY_SIGNAL = 'UNNAMED_41_ICXC7Z010_I26_PSDD_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICMT41K256M16_I99_ZQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_41_ICMT41K256M16_I99_ZQ';
PHY_SIGNAL = 'UNNAMED_41_ICMT41K256M16_I99_ZQ';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '42';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I1@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C663';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 LONG_PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I2@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C665';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I3@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C667';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I4@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C669';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I6@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C671';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C678';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I13@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I14@RESISTORS.RES(CHIPS)';
LOCATION   = 'R685';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I16@RESISTORS.RES(CHIPS)';
LOCATION   = 'R681';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I17@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C684';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I18@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C688';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I20@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C675';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I21@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E677';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-600OHMS,25,E007179,L0603-(),L0603';
 LONG_PART_NAME = 'FERRITE_SM-600OHMS,25,E007179,L0603-(),L0603';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-600OHMS,25,E007179,L0603';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-600OHMS,25,E007179,L0603';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I22@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C680';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I24@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C686';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I25@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C676';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 LONG_PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I26@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C679';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I28@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C683';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I30@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C664';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I31@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C666';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I33@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C668';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I34@RESISTORS.RES(CHIPS)';
LOCATION   = 'R689';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I36@TRANSISTORS.TRANNMOSFET_V8(CHIPS)';
LOCATION   = 'Q512';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/trannmosfet_v8/chips/chips.prt';
 PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 LONG_PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 PARENT_PPT_PHYS_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_PPT = 'TRANNMOSFET_V8';
 PARENT_PPT_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_CHIPS_PHYS_PART = 'TRANNMOSFET_V8_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I37@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C670';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 LONG_PART_NAME = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71-(),C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-100UF,6.3V,20,E016591,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I38@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C672';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I39@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C673';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I41@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C674';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I48@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '7';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I53@CONN_PCB.CN10P_ODD_EVEN(CHIPS)';
LOCATION   = 'P510';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn10p_odd_even/chips/chips.prt';
 PART_NAME = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219-CNHDR2X5H219';
 LONG_PART_NAME = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219-CNHDR2X5H219';
 PARENT_PPT_PHYS_PART = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219';
 PARENT_PPT = 'CN10P_ODD_EVEN';
 PARENT_PPT_PART = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219';
 PARENT_CHIPS_PHYS_PART = 'CN10P_ODD_EVEN_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I54@CONN_PCB.CN10P_ODD_EVEN(CHIPS)';
LOCATION   = 'P510';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn10p_odd_even/chips/chips.prt';
 PART_NAME = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219-CNHDR2X5H219';
 LONG_PART_NAME = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219-CNHDR2X5H219';
 PARENT_PPT_PHYS_PART = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219';
 PARENT_PPT = 'CN10P_ODD_EVEN';
 PARENT_PPT_PART = 'CN10P_ODD_EVEN_TH-FTSH-105-01-L-D,E018623,CNHDR2X5H219';
 PARENT_CHIPS_PHYS_PART = 'CN10P_ODD_EVEN_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I60@DIODES.DIOLED(CHIPS)';
LOCATION   = 'DS11';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioled/chips/chips.prt';
 PART_NAME = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804-LED0804,LED0804_RA';
 LONG_PART_NAME = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804-LED0804,LED0804_RA';
 PARENT_PPT_PHYS_PART = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804';
 PARENT_PPT = 'DIOLED';
 PARENT_PPT_PART = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804';
 PARENT_CHIPS_PHYS_PART = 'DIOLED_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I61@RESISTORS.RES(CHIPS)';
LOCATION   = 'R691';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I66@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C692';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I67@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E687';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 LONG_PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I68@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E682';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 LONG_PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I72@TRANSISTORS.TRANNMOSFET_V8(CHIPS)';
LOCATION   = 'Q2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/trannmosfet_v8/chips/chips.prt';
 PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 LONG_PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 PARENT_PPT_PHYS_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_PPT = 'TRANNMOSFET_V8';
 PARENT_PPT_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_CHIPS_PHYS_PART = 'TRANNMOSFET_V8_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I73@RESISTORS.RES(CHIPS)';
LOCATION   = 'R215';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I74@DIODES.DIOLED(CHIPS)';
LOCATION   = 'DS12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioled/chips/chips.prt';
 PART_NAME = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804-LED0804,LED0804_RA';
 LONG_PART_NAME = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804-LED0804,LED0804_RA';
 PARENT_PPT_PHYS_PART = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804';
 PARENT_PPT = 'DIOLED';
 PARENT_PPT_PART = 'DIOLED_SM-LTST-S220TBKT,3.3V,N/A,E026167,LED0804';
 PARENT_CHIPS_PHYS_PART = 'DIOLED_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I79@RESISTORS.RES(CHIPS)';
LOCATION   = 'R216';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I81@TRANSISTORS.TRANNMOSFET_V8(CHIPS)';
LOCATION   = 'Q1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/trannmosfet_v8/chips/chips.prt';
 PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 LONG_PART_NAME = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23-SOT23';
 PARENT_PPT_PHYS_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_PPT = 'TRANNMOSFET_V8';
 PARENT_PPT_PART = 'TRANNMOSFET_V8_SM-BSS138LT1G,E018770,SOT23';
 PARENT_CHIPS_PHYS_PART = 'TRANNMOSFET_V8_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I82@RESISTORS.RES(CHIPS)';
LOCATION   = 'R130';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I84@RESISTORS.RES(CHIPS)';
LOCATION   = 'R214';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I86@RESISTORS.RES(CHIPS)';
LOCATION   = 'R213';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-2.49K,E007345,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-2.49K,E007345,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-2.49K,E007345,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-2.49K,E007345,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE42_I87@RESISTORS.RES(CHIPS)';
LOCATION   = 'R148';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_CAP_I17_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_CAP_I17_N1';
PHY_SIGNAL = 'UNNAMED_42_CAP_I17_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_CAP_I17_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_CAP_I17_N2';
PHY_SIGNAL = 'UNNAMED_42_CAP_I17_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_DIOLED_I60_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_DIOLED_I60_N';
PHY_SIGNAL = 'UNNAMED_42_DIOLED_I60_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_DONE0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_DONE0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_DONE0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_INITB0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_INITB0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_INITB0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_PROGRAMB0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_PROGRAMB0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_PROGRA';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_VCCBATT0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_VCCBATT0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_VCCBAT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_RES_I61_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_RES_I61_N2';
PHY_SIGNAL = 'UNNAMED_42_RES_I61_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_DIOLED_I74_N';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_DIOLED_I74_N';
PHY_SIGNAL = 'UNNAMED_42_DIOLED_I74_N';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_VP0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_VP0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_VP0';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_RES_I73_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_RES_I73_N2';
PHY_SIGNAL = 'UNNAMED_42_RES_I73_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_CFGBVS0';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_ICXC7Z010_I13_CFGBVS0';
PHY_SIGNAL = 'UNNAMED_42_ICXC7Z010_I13_CFGBVS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_TRANNMOSFETV8_I36_D';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_42_TRANNMOSFETV8_I36_D';
PHY_SIGNAL = 'UNNAMED_42_TRANNMOSFETV8_I36_D';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '45';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I250@DIODES.DIO(CHIPS)';
LOCATION   = 'D739';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio/chips/chips.prt';
 PART_NAME = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201-D0201';
 LONG_PART_NAME = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201-D0201';
 PARENT_PPT_PHYS_PART = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201';
 PARENT_PPT = 'DIO';
 PARENT_PPT_PART = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201';
 PARENT_CHIPS_PHYS_PART = 'DIO_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I251@DIODES.DIO(CHIPS)';
LOCATION   = 'D741';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dio/chips/chips.prt';
 PART_NAME = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201-D0201';
 LONG_PART_NAME = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201-D0201';
 PARENT_PPT_PHYS_PART = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201';
 PARENT_PPT = 'DIO';
 PARENT_PPT_PART = 'DIO_SM-SESD0201X1UN-0020-09,9V,N/A,E022225,D0201';
 PARENT_CHIPS_PHYS_PART = 'DIO_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I254@RESISTORS.RES(CHIPS)';
LOCATION   = 'R744';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402';
 LONG_PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402';
 PARENT_PPT_PHYS_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I255@CONN_PCB.CN5P_3SHLD(CHIPS)';
LOCATION   = 'P516';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn5p_3shld/chips/chips.prt';
 PART_NAME = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001-CNMOLEX47590-0001';
 LONG_PART_NAME = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001-CNMOLEX47590-0001';
 PARENT_PPT_PHYS_PART = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001';
 PARENT_PPT = 'CN5P_3SHLD';
 PARENT_PPT_PART = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001';
 PARENT_CHIPS_PHYS_PART = 'CN5P_3SHLD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I256@CONN_PCB.CN5P_3SHLD(CHIPS)';
LOCATION   = 'P519';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/conn_pcb/cn5p_3shld/chips/chips.prt';
 PART_NAME = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001-CNMOLEX47590-0001';
 LONG_PART_NAME = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001-CNMOLEX47590-0001';
 PARENT_PPT_PHYS_PART = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001';
 PARENT_PPT = 'CN5P_3SHLD';
 PARENT_PPT_PART = 'CN5P_3SHLD_SM-47590-0001,E015753,CNMOLEX47590-0001';
 PARENT_CHIPS_PHYS_PART = 'CN5P_3SHLD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I257@RESISTORS.RES(CHIPS)';
LOCATION   = 'R749';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402';
 LONG_PART_NAME = 'RES_SM-1K,E003763,1/10W,1,R0402-R0402';
 PARENT_PPT_PHYS_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-1K,E003763,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I317@IC_ADI.ADP198(CHIPS)';
LOCATION   = 'U16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp198/chips/chips.prt';
 PART_NAME = 'ADP198_SM-ADP198ACBZ-11,E024730,WLCSP4-2-WLCSP4-2';
 LONG_PART_NAME = 'ADP198_SM-ADP198ACBZ-11,E024730,WLCSP4-2-WLCSP4-2';
 PARENT_PPT_PHYS_PART = 'ADP198_SM-ADP198ACBZ-11,E024730,WLCSP4-2';
 PARENT_PPT = 'ADP198';
 PARENT_PPT_PART = 'ADP198_SM-ADP198ACBZ-11,E024730,WLCSP4-2';
 PARENT_CHIPS_PHYS_PART = 'ADP198_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I323@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C280';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-2.2UF,10V,10,E017584,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-2.2UF,10V,10,E017584,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-2.2UF,10V,10,E017584,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-2.2UF,10V,10,E017584,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I331@INDUCTORS.CHOKE4P(CHIPS)';
LOCATION   = 'L1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/choke4p/chips/chips.prt';
 PART_NAME = 'CHOKE4P_SM-90OHMS AT 100MEGHZ,25,E027226,L0805-4PH39-L0805-4PH39';
 LONG_PART_NAME = 'CHOKE4P_SM-90OHMS AT 100MEGHZ,25,E027226,L0805-4PH39-L0805-4PH39';
 PARENT_PPT_PHYS_PART = 'CHOKE4P_SM-90OHMS AT 100MEGHZ,25,E027226,L0805-4PH39';
 PARENT_PPT = 'CHOKE4P';
 PARENT_PPT_PART = 'CHOKE4P_SM-90OHMS AT 100MEGHZ,25,E027226,L0805-4PH39';
 PARENT_CHIPS_PHYS_PART = 'CHOKE4P_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I379@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TMS';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I380@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TCK';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I381@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TDO';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I382@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TDI';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I383@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'RX';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I384@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'TX';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I385@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'IO3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I386@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I387@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I390@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'CALIB_REF1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I391@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'CALIB_REF2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I392@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '3V3_A';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I393@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'VIN';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I394@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '1V8_D';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I395@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '1V35';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I396@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'VCCPINT';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I397@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '3V3_D';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I398@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '6V0_A';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I399@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '-6V0_A';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I401@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '-3V3_A';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I403@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I404@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I406@IC_LIN.LINLTC4415(CHIPS)';
LOCATION   = 'U21';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_lin/linltc4415/chips/chips.prt';
 PART_NAME = 'LINLTC4415_SM-LTC4415EDHC#PBF,E027541,DFN16_5X3_PAD4_4X1_65-DFN16_5X3_PAD4_4X1_65';
 LONG_PART_NAME = 'LINLTC4415_SM-LTC4415EDHC#PBF,E027541,DFN16_5X3_PAD4_4X1_65-DFN16_5X3_PAD4_4X1_65';
 PARENT_PPT_PHYS_PART = 'LINLTC4415_SM-LTC4415EDHC#PBF,E027541,DFN16_5X3_PAD4_4X1_65';
 PARENT_PPT = 'LINLTC4415';
 PARENT_PPT_PART = 'LINLTC4415_SM-LTC4415EDHC#PBF,E027541,DFN16_5X3_PAD4_4X1_65';
 PARENT_CHIPS_PHYS_PART = 'LINLTC4415_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I410@RESISTORS.RES(CHIPS)';
LOCATION   = 'R192';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-470,E014032,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-470,E014032,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I416@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C312';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I417@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C313';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I420@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C320';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I421@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C321';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I424@RESISTORS.RES(CHIPS)';
LOCATION   = 'R195';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I425@RESISTORS.RES(CHIPS)';
LOCATION   = 'R196';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I426@RESISTORS.RES(CHIPS)';
LOCATION   = 'R166';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-27.4K,E021819,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-27.4K,E021819,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-27.4K,E021819,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-27.4K,E021819,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I428@RESISTORS.RES(CHIPS)';
LOCATION   = 'R190';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.06K,E021385,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.06K,E021385,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I429@RESISTORS.RES(CHIPS)';
LOCATION   = 'R189';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100,E003760,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-100,E003760,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-100,E003760,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-100,E003760,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I430@RESISTORS.RES(CHIPS)';
LOCATION   = 'R212';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I431@RESISTORS.RES(CHIPS)';
LOCATION   = 'R191';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-240,E010877,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-240,E010877,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-240,E010877,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-240,E010877,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I432@INDUCTORS.CHOKE4P(CHIPS)';
LOCATION   = 'L10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/choke4p/chips/chips.prt';
 PART_NAME = 'CHOKE4P_SM-190OHMS AT 100MEGHZ,N/A,E019844,L2020_A-L2020_A';
 LONG_PART_NAME = 'CHOKE4P_SM-190OHMS AT 100MEGHZ,N/A,E019844,L2020_A-L2020_A';
 PARENT_PPT_PHYS_PART = 'CHOKE4P_SM-190OHMS AT 100MEGHZ,N/A,E019844,L2020_A';
 PARENT_PPT = 'CHOKE4P';
 PARENT_PPT_PART = 'CHOKE4P_SM-190OHMS AT 100MEGHZ,N/A,E019844,L2020_A';
 PARENT_CHIPS_PHYS_PART = 'CHOKE4P_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I433@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C281';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I434@FUSES.FSFUSE(CHIPS)';
LOCATION   = 'F1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/fuses/fsfuse/chips/chips.prt';
 PART_NAME = 'FSFUSE_SM-0.5A,6V,E016128,F0805-F0805';
 LONG_PART_NAME = 'FSFUSE_SM-0.5A,6V,E016128,F0805-F0805';
 PARENT_PPT_PHYS_PART = 'FSFUSE_SM-0.5A,6V,E016128,F0805';
 PARENT_PPT = 'FSFUSE';
 PARENT_PPT_PART = 'FSFUSE_SM-0.5A,6V,E016128,F0805';
 PARENT_CHIPS_PHYS_PART = 'FSFUSE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I435@RESISTORS.RES(CHIPS)';
LOCATION   = 'R156';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I436@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C324';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I438@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = '4V0_A';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 LONG_PART_NAME = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40-TPSMC40';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_SM-TESTPAD,E019801,TPSMC40';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I439@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C326';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE45_I441@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C325';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PGND';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PGND';
PHY_SIGNAL = 'PGND';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CN5P3SHLD_I255_N6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CN5P3SHLD_I255_N6';
PHY_SIGNAL = 'UNNAMED_45_CN5P3SHLD_I255_N6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CN5P3SHLD_I256_N6';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CN5P3SHLD_I256_N6';
PHY_SIGNAL = 'UNNAMED_45_CN5P3SHLD_I256_N6';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_ADP198_I317_VOUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_ADP198_I317_VOUT';
PHY_SIGNAL = 'UNNAMED_45_ADP198_I317_VOUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CHOKE4P_I331_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CHOKE4P_I331_N2';
PHY_SIGNAL = 'UNNAMED_45_CHOKE4P_I331_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CHOKE4P_I331_N3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CHOKE4P_I331_N3';
PHY_SIGNAL = 'UNNAMED_45_CHOKE4P_I331_N3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_LINLTC4415_I406_CLIM1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_LINLTC4415_I406_CLIM1';
PHY_SIGNAL = 'UNNAMED_45_LINLTC4415_I406_CLIM';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_LINLTC4415_I406_CLIM2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_LINLTC4415_I406_CLIM2';
PHY_SIGNAL = 'UNNAMED_45_LINLTC4415_I406_CL_1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CAP_I416_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_45_CAP_I416_N1';
PHY_SIGNAL = 'UNNAMED_45_CAP_I416_N1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '43';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I1@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I2@IC_OTHER.ICXC7Z010(CHIPS)';
LOCATION   = 'U511';
SEC = '2';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_other/icxc7z010/chips/chips.prt';
 PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 LONG_PART_NAME = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225-CSPBGA225';
 PARENT_PPT_PHYS_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_PPT = 'ICXC7Z010';
 PARENT_PPT_PART = 'ICXC7Z010_SM-XC7Z010-1CLG225C4334,E025809,CSPBGA225';
 PARENT_CHIPS_PHYS_PART = 'ICXC7Z010_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I3@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C696';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I4@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C698';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I5@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C697';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I6@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C699';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I7@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C700';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I8@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C702';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I9@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C704';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C706';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I12@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C708';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I13@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C710';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I15@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C701';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I16@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C703';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I17@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C705';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I18@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C707';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I20@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C709';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.47UF,10V,10,E007611,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.47UF,10V,10,E007611,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I21@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C711';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I23@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C712';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I24@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C713';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I25@IC_ADI.ADP5589_V2(CHIPS)';
LOCATION   = 'U15';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp5589_v2/chips/chips.prt';
 PART_NAME = 'ADP5589_V2_SM-ADP5589ACPZ-00,E024896,QFN24_3_5X3_5_PAD2_2X2_2-QFN24_3_5X3_5_PAD2_2X2_2';
 LONG_PART_NAME = 'ADP5589_V2_SM-ADP5589ACPZ-00,E024896,QFN24_3_5X3_5_PAD2_2X2_2-QFN24_3_5X3_5_PAD2_2X2_2';
 PARENT_PPT_PHYS_PART = 'ADP5589_V2_SM-ADP5589ACPZ-00,E024896,QFN24_3_5X3_5_PAD2_2X2_2';
 PARENT_PPT = 'ADP5589_V2';
 PARENT_PPT_PART = 'ADP5589_V2_SM-ADP5589ACPZ-00,E024896,QFN24_3_5X3_5_PAD2_2X2_2';
 PARENT_CHIPS_PHYS_PART = 'ADP5589_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I29@RESISTORS.RES(CHIPS)';
LOCATION   = 'R87';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I40@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C240';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I46@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I49@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I51@NOCOMPONENT.NCTESTPAD(CHIPS)';
LOCATION   = 'GND_4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/nocomponent/nctestpad/chips/chips.prt';
 PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 LONG_PART_NAME = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30-TPC50D30';
 PARENT_PPT_PHYS_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_PPT = 'NCTESTPAD';
 PARENT_PPT_PART = 'NCTESTPAD_TH-TESTPAD,E007450,TPC50D30';
 PARENT_CHIPS_PHYS_PART = 'NCTESTPAD_TH';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I52@RESISTORS.RES(CHIPS)';
LOCATION   = 'R210';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I53@RESISTORS.RES(CHIPS)';
LOCATION   = 'R211';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE43_I54@RESISTORS.RES(CHIPS)';
LOCATION   = 'R217';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_43_ADP5589V2_I25_RSTN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_43_ADP5589V2_I25_RSTN';
PHY_SIGNAL = 'UNNAMED_43_ADP5589V2_I25_RSTN';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '37';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I60@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I199@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I200@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I201@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C204';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I203@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I204@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C205';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I206@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C206';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I211@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I212@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C198';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-9.09K,E003770,1/16W,1,R0402-R0402,R0402L_ALT';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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 PARENT_PPT = 'CAP';
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END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
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 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
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 PARENT_PPT = 'CAP';
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END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
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END_LIB_INFO;
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BEGIN_LIB_INFO:
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 PARENT_PPT = 'CAP';
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
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BEGIN_LIB_INFO:
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END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'C177';
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'C19';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'R67';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-3.83K,E020197,1/16W,0.1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-3.83K,E020197,1/16W,0.1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-3.83K,E020197,1/16W,0.1,R0402';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10PF,50V,5,E007982,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10PF,50V,5,E007982,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
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 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
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 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-C0201';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-15NF,35V,10,E033385,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-15NF,35V,10,E033385,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-15NF,35V,10,E033385,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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LOCATION   = 'U12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp1614/chips/chips.prt';
 PART_NAME = 'ADP1614_SM-ADP1614ACPZ,E025247,QFN10_3X3_PAD2_38X1_64-QFN10_3X3_PAD2_38X1_64';
 LONG_PART_NAME = 'ADP1614_SM-ADP1614ACPZ,E025247,QFN10_3X3_PAD2_38X1_64-QFN10_3X3_PAD2_38X1_64';
 PARENT_PPT_PHYS_PART = 'ADP1614_SM-ADP1614ACPZ,E025247,QFN10_3X3_PAD2_38X1_64';
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 PARENT_PPT_PART = 'ADP1614_SM-ADP1614ACPZ,E025247,QFN10_3X3_PAD2_38X1_64';
 PARENT_CHIPS_PHYS_PART = 'ADP1614_SM';
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LOCATION   = 'C16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'R68';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-1,E010031,1/16W,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-1,E010031,1/16W,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-1,E010031,1/16W,5,R0402';
 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'C18';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I269@RESISTORS.RES(CHIPS)';
LOCATION   = 'R69';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-43.2K,E018504,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-43.2K,E018504,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-43.2K,E018504,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-43.2K,E018504,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I270@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-4.7UH,20,E013623,LSMSQ157H122-LSMSQ157H122';
 LONG_PART_NAME = 'IND_SM-4.7UH,20,E013623,LSMSQ157H122-LSMSQ157H122';
 PARENT_PPT_PHYS_PART = 'IND_SM-4.7UH,20,E013623,LSMSQ157H122';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-4.7UH,20,E013623,LSMSQ157H122';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I271@RESISTORS.RES(CHIPS)';
LOCATION   = 'R73';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-165K,E026053,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-165K,E026053,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-165K,E026053,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-165K,E026053,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I272@DIODES.DIOSCHOTTKY(CHIPS)';
LOCATION   = 'D25';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioschottky/chips/chips.prt';
 PART_NAME = 'DIOSCHOTTKY_SM-MBR130LSFT1G,30V,N/A,E016634,SOD123FL-SOD123FL';
 LONG_PART_NAME = 'DIOSCHOTTKY_SM-MBR130LSFT1G,30V,N/A,E016634,SOD123FL-SOD123FL';
 PARENT_PPT_PHYS_PART = 'DIOSCHOTTKY_SM-MBR130LSFT1G,30V,N/A,E016634,SOD123FL';
 PARENT_PPT = 'DIOSCHOTTKY';
 PARENT_PPT_PART = 'DIOSCHOTTKY_SM-MBR130LSFT1G,30V,N/A,E016634,SOD123FL';
 PARENT_CHIPS_PHYS_PART = 'DIOSCHOTTKY_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I275@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-110NH,5,E016398,L9075-L9075';
 LONG_PART_NAME = 'IND_SM-110NH,5,E016398,L9075-L9075';
 PARENT_PPT_PHYS_PART = 'IND_SM-110NH,5,E016398,L9075';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-110NH,5,E016398,L9075';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I277@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C99';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 LONG_PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I279@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C101';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 LONG_PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I281@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C176';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I284@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C213';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I286@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C212';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I287@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E17';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I289@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C214';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I290@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I291@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E18';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I302@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I309@RESISTORS.RES(CHIPS)';
LOCATION   = 'R164';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-15K,E007441,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-15K,E007441,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-15K,E007441,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-15K,E007441,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I311@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C311';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I312@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C310';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I315@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C23';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 LONG_PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805-2,C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I317@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I318@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 LONG_PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-100OHM,25,E012241,L0805';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I319@RESISTORS.RES(CHIPS)';
LOCATION   = 'R165';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-6.49K,E026140,1/10W,1,R0402-R0402';
 LONG_PART_NAME = 'RES_SM-6.49K,E026140,1/10W,1,R0402-R0402';
 PARENT_PPT_PHYS_PART = 'RES_SM-6.49K,E026140,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-6.49K,E026140,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE37_I320@IC_LIN.LINLT1761(CHIPS)';
LOCATION   = 'U17';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_lin/linlt1761/chips/chips.prt';
 PART_NAME = 'LINLT1761_SM-LT1761ES5-SD#TRMPBF,E031208,TSOT-5-TSOT-5';
 LONG_PART_NAME = 'LINLT1761_SM-LT1761ES5-SD#TRMPBF,E031208,TSOT-5-TSOT-5';
 PARENT_PPT_PHYS_PART = 'LINLT1761_SM-LT1761ES5-SD#TRMPBF,E031208,TSOT-5';
 PARENT_PPT = 'LINLT1761';
 PARENT_PPT_PART = 'LINLT1761_SM-LT1761ES5-SD#TRMPBF,E031208,TSOT-5';
 PARENT_CHIPS_PHYS_PART = 'LINLT1761_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):GND';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):GND';
PHY_SIGNAL = 'GND';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP237X_I231_FB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP237X_I231_FB';
PHY_SIGNAL = 'UNNAMED_37_ADP237X_I231_FB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP237X_I231_SW';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP237X_I231_SW';
PHY_SIGNAL = 'UNNAMED_37_ADP237X_I231_SW';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I212_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I212_N1';
PHY_SIGNAL = 'UNNAMED_37_CAP_I212_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I222_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I222_N1';
PHY_SIGNAL = 'UNNAMED_37_CAP_I222_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I222_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I222_N2';
PHY_SIGNAL = 'UNNAMED_37_CAP_I222_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_CLRES';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_CLRES';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_CLRES';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_COMP';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_COMP';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_COMP';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_FB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_FB';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_FB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_SS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_SS';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_SS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_SW1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_SW1';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_SW1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_VIN';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_ADP1614_I262_VIN';
PHY_SIGNAL = 'UNNAMED_37_ADP1614_I262_VIN';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I260_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I260_N2';
PHY_SIGNAL = 'UNNAMED_37_CAP_I260_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I315_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_CAP_I315_N1';
PHY_SIGNAL = 'UNNAMED_37_CAP_I315_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_LINLT1761_I320_ADJ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_37_LINLT1761_I320_ADJ';
PHY_SIGNAL = 'UNNAMED_37_LINLT1761_I320_ADJ';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '38';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I322@RESISTORS.RES(CHIPS)';
LOCATION   = 'R155';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-(),R0402';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-(),R0402';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I349@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C738';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I350@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C742';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I352@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C737';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I353@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C740';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I355@RESISTORS.RES(CHIPS)';
LOCATION   = 'R747';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.7K,E008190,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7K,E008190,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I356@RESISTORS.RES(CHIPS)';
LOCATION   = 'R743';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-27.4K,E021819,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-27.4K,E021819,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-27.4K,E021819,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-27.4K,E021819,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I357@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C746';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.047UF,25V,10,E025704,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.047UF,25V,10,E025704,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I358@IC_ADI.ADP2114(CHIPS)';
LOCATION   = 'U518';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp2114/chips/chips.prt';
 PART_NAME = 'ADP2114_SM-ADP2114ACPZ,E008105,QFN32_5X5_PAD3_1X3_1-QFN32_5X5_PAD3_1X3_1';
 LONG_PART_NAME = 'ADP2114_SM-ADP2114ACPZ,E008105,QFN32_5X5_PAD3_1X3_1-QFN32_5X5_PAD3_1X3_1';
 PARENT_PPT_PHYS_PART = 'ADP2114_SM-ADP2114ACPZ,E008105,QFN32_5X5_PAD3_1X3_1';
 PARENT_PPT = 'ADP2114';
 PARENT_PPT_PART = 'ADP2114_SM-ADP2114ACPZ,E008105,QFN32_5X5_PAD3_1X3_1';
 PARENT_CHIPS_PHYS_PART = 'ADP2114_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I359@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C745';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.047UF,25V,10,E025704,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.047UF,25V,10,E025704,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I360@RESISTORS.RES(CHIPS)';
LOCATION   = 'R517';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10,E013982,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-10,E013982,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-10,E013982,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10,E013982,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I361@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C748';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I363@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L520';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-1.5UH,20,E017267,LSMSQ157H83-LSMSQ157H83';
 LONG_PART_NAME = 'IND_SM-1.5UH,20,E017267,LSMSQ157H83-LSMSQ157H83';
 PARENT_PPT_PHYS_PART = 'IND_SM-1.5UH,20,E017267,LSMSQ157H83';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-1.5UH,20,E017267,LSMSQ157H83';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I365@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C756';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-180PF,50V,5,E033222,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-180PF,50V,5,E033222,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-180PF,50V,5,E033222,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-180PF,50V,5,E033222,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I366@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C757';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.0033UF,50V,10,E007461,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.0033UF,50V,10,E007461,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.0033UF,50V,10,E007461,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.0033UF,50V,10,E007461,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I368@RESISTORS.RES(CHIPS)';
LOCATION   = 'R760';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I370@RESISTORS.RES(CHIPS)';
LOCATION   = 'R764';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-14.3K,E014068,1/20W,1,R0201-R0201';
 LONG_PART_NAME = 'RES_SM-14.3K,E014068,1/20W,1,R0201-R0201';
 PARENT_PPT_PHYS_PART = 'RES_SM-14.3K,E014068,1/20W,1,R0201';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-14.3K,E014068,1/20W,1,R0201';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I371@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C754';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I374@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C758';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I377@RESISTORS.RES(CHIPS)';
LOCATION   = 'R763';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-17.8K,E011033,1/10W,1,R0603-R0603,R0603L';
 LONG_PART_NAME = 'RES_SM-17.8K,E011033,1/10W,1,R0603-R0603,R0603L';
 PARENT_PPT_PHYS_PART = 'RES_SM-17.8K,E011033,1/10W,1,R0603';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-17.8K,E011033,1/10W,1,R0603';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I379@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C761';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I381@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C762';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I383@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L521';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-1.5UH,20,E017267,LSMSQ157H83-LSMSQ157H83';
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 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I385@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C751';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-150PF,50V,5,E012646,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-150PF,50V,5,E012646,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I386@RESISTORS.RES(CHIPS)';
LOCATION   = 'R752';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10K,E003751,1/10W,1,R0402-R0402,R0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'RES_SM-10K,E003751,1/10W,1,R0402';
 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

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PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I387@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C753';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-5.6NF,50V,5,E033450,C0402H22-C0402H22,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-5.6NF,50V,5,E033450,C0402H22-C0402H22,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-5.6NF,50V,5,E033450,C0402H22';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I391@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E767';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-100OHM,25,E012241,L0805-L0805';
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 PARENT_PPT = 'FERRITE';
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 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I392@CAPACITORS.CAP(CHIPS)';
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'R766';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-23.2K,E019517,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-23.2K,E019517,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-23.2K,E019517,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-23.2K,E019517,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I395@RESISTORS.RES(CHIPS)';
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-46.4K,E011115,1/16W,1,R0402-R0402,R0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'RES_SM-46.4K,E011115,1/16W,1,R0402';
 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
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 PARENT_PPT = 'FERRITE';
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 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
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 PARENT_PPT = 'FERRITE';
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 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
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END_LIB_INFO;
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
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 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60-C0805H60';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,6.3V,20,E008247,C0805H60';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'R89';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100K,E003796,1/16W,1,R0402-R0402,R0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'RES_SM-100K,E003796,1/16W,1,R0402';
 PARENT_PPT = 'RES';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'R88';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10,E013982,1/20W,1,R0201-R0201';
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 PARENT_PPT_PHYS_PART = 'RES_SM-10,E013982,1/20W,1,R0201';
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 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'C193';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-0.047UF,25V,10,E025704,C0402';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'U6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp2114/chips/chips.prt';
 PART_NAME = 'ADP2114_SM-ADP2114ACPZ,E008105,QFN32_5X5_PAD3_1X3_1-QFN32_5X5_PAD3_1X3_1';
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 PARENT_CHIPS_PHYS_PART = 'ADP2114_SM';
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LOCATION   = 'C194';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.047UF,25V,10,E025704,C0402-C0402,C0402L_ALT';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
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LOCATION   = 'C187';
SEC = '1';

BEGIN_LIB_INFO:
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 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
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LOCATION   = 'C190';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'C178';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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LOCATION   = 'C183';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603,C0603L_ALT';
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 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
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 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

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SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-5.6UH,20,E027225,LSMSQ154H47_A-LSMSQ154H47_A';
 LONG_PART_NAME = 'IND_SM-5.6UH,20,E027225,LSMSQ154H47_A-LSMSQ154H47_A';
 PARENT_PPT_PHYS_PART = 'IND_SM-5.6UH,20,E027225,LSMSQ154H47_A';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-5.6UH,20,E027225,LSMSQ154H47_A';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I456@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-1UH,20,E015845,LSMSQ157H83-LSMSQ157H83';
 LONG_PART_NAME = 'IND_SM-1UH,20,E015845,LSMSQ157H83-LSMSQ157H83';
 PARENT_PPT_PHYS_PART = 'IND_SM-1UH,20,E015845,LSMSQ157H83';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-1UH,20,E015845,LSMSQ157H83';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I457@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C215';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
 LONG_PART_NAME = 'CAP_SM-22UF,25V,20,E032575,C0805H60-C0805H60';
 PARENT_PPT_PHYS_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-22UF,25V,20,E032575,C0805H60';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I458@RESISTORS.RES(CHIPS)';
LOCATION   = 'R74';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I459@RESISTORS.RES(CHIPS)';
LOCATION   = 'R75';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-8.25K,E013600,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-8.25K,E013600,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I460@RESISTORS.RES(CHIPS)';
LOCATION   = 'R90';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-15K,E007441,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-15K,E007441,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-15K,E007441,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-15K,E007441,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I461@RESISTORS.RES(CHIPS)';
LOCATION   = 'R204';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-4.99K,E006643,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.99K,E006643,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I462@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C197';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I463@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C207';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.0012UF,25V,5,E012597,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.0012UF,25V,5,E012597,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.0012UF,25V,5,E012597,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.0012UF,25V,5,E012597,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I464@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C199';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-120PF,25V,5,E012600,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-120PF,25V,5,E012600,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-120PF,25V,5,E012600,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-120PF,25V,5,E012600,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I465@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C203';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.0022UF,50V,10,E007460,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-0.0022UF,50V,10,E007460,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.0022UF,50V,10,E007460,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.0022UF,50V,10,E007460,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I466@RESISTORS.RES(CHIPS)';
LOCATION   = 'R206';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I467@RESISTORS.RES(CHIPS)';
LOCATION   = 'R205';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I468@RESISTORS.RES(CHIPS)';
LOCATION   = 'R91';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I469@RESISTORS.RES(CHIPS)';
LOCATION   = 'R149';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I470@RESISTORS.RES(CHIPS)';
LOCATION   = 'R92';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-82.5K,E025324,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-82.5K,E025324,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-82.5K,E025324,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-82.5K,E025324,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I471@RESISTORS.RES(CHIPS)';
LOCATION   = 'R203';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-47.5K,E013598,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-47.5K,E013598,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-47.5K,E013598,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-47.5K,E013598,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I474@RESISTORS.RES(CHIPS)';
LOCATION   = 'R207';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-16.2K,E022435,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-16.2K,E022435,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-16.2K,E022435,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-16.2K,E022435,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I475@RESISTORS.RES(CHIPS)';
LOCATION   = 'R208';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-24.3K,E024557,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-24.3K,E024557,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-24.3K,E024557,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-24.3K,E024557,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I476@RESISTORS.RES(CHIPS)';
LOCATION   = 'R209';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE38_I477@RESISTORS.RES(CHIPS)';
LOCATION   = 'R750';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_FREQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_FREQ';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_FREQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_OPCFG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_OPCFG';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_OPCFG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SS1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SS1';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_SS1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SS2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SS2';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_SS2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SW1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SW1';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_SW1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SW3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I358_SW3';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I358_SW3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_FREQ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_FREQ';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_FREQ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_OPCFG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_OPCFG';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_OPCFG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SS1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SS1';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_SS1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SS2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SS2';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_SS2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SW1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SW1';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_SW1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SW3';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_SW3';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_SW3';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I366_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I366_N2';
PHY_SIGNAL = 'UNNAMED_38_CAP_I366_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I379_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I379_N1';
PHY_SIGNAL = 'UNNAMED_38_CAP_I379_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I387_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I387_N2';
PHY_SIGNAL = 'UNNAMED_38_CAP_I387_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_V1SET';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_V1SET';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_V1SET';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_V2SET';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_ADP2114_I447_V2SET';
PHY_SIGNAL = 'UNNAMED_38_ADP2114_I447_V2SET';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I457_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I457_N1';
PHY_SIGNAL = 'UNNAMED_38_CAP_I457_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I463_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I463_N1';
PHY_SIGNAL = 'UNNAMED_38_CAP_I463_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I465_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_38_CAP_I465_N2';
PHY_SIGNAL = 'UNNAMED_38_CAP_I465_N2';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '16';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I122@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C217';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I126@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C218';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I127@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E19';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I128@RESISTORS.RES(CHIPS)';
LOCATION   = 'R78';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-120K,E015615,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-120K,E015615,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-120K,E015615,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-120K,E015615,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I129@RESISTORS.RES(CHIPS)';
LOCATION   = 'R77';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-69.8K,E019611,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-69.8K,E019611,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-69.8K,E019611,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-69.8K,E019611,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I131@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C222';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I135@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C221';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I138@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E24';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I139@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E22';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I178@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C182';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 LONG_PART_NAME = 'CAP_SM-33PF,50V,5,E000396,C0603-C0603,C0603L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-33PF,50V,5,E000396,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I180@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-2200PF,50V,10,E024338,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-2200PF,50V,10,E024338,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-2200PF,50V,10,E024338,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-2200PF,50V,10,E024338,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I184@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603';
 LONG_PART_NAME = 'CAP_SM-10UF,10V,20,E022682,C0603-C0603';
 PARENT_PPT_PHYS_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-10UF,10V,20,E022682,C0603';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I186@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C3';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I188@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C6';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I189@IC_ADI.ADP5074(CHIPS)';
LOCATION   = 'U10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp5074/chips/chips.prt';
 PART_NAME = 'ADP5074_SM-ADP5074ACPZ,E023965,QFN16_3X3_PAD1_7X1_7-QFN16_3X3_PAD1_7X1_7';
 LONG_PART_NAME = 'ADP5074_SM-ADP5074ACPZ,E023965,QFN16_3X3_PAD1_7X1_7-QFN16_3X3_PAD1_7X1_7';
 PARENT_PPT_PHYS_PART = 'ADP5074_SM-ADP5074ACPZ,E023965,QFN16_3X3_PAD1_7X1_7';
 PARENT_PPT = 'ADP5074';
 PARENT_PPT_PART = 'ADP5074_SM-ADP5074ACPZ,E023965,QFN16_3X3_PAD1_7X1_7';
 PARENT_CHIPS_PHYS_PART = 'ADP5074_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I191@RESISTORS.RES(CHIPS)';
LOCATION   = 'R2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-100K,E003796,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-100K,E003796,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-100K,E003796,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-100K,E003796,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I194@RESISTORS.RES(CHIPS)';
LOCATION   = 'R8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-0,E003438,N/A,5,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-0,E003438,N/A,5,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I196@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L2';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-3UH,30,E026905,LSMSQ228H118_A-LSMSQ228H118_A';
 LONG_PART_NAME = 'IND_SM-3UH,30,E026905,LSMSQ228H118_A-LSMSQ228H118_A';
 PARENT_PPT_PHYS_PART = 'IND_SM-3UH,30,E026905,LSMSQ228H118_A';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-3UH,30,E026905,LSMSQ228H118_A';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I198@DIODES.DIOSCHOTTKY(CHIPS)';
LOCATION   = 'D24';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioschottky/chips/chips.prt';
 PART_NAME = 'DIOSCHOTTKY_SM-PD3S140-7,60V,N/A,E017965,POWERDI323-POWERDI323';
 LONG_PART_NAME = 'DIOSCHOTTKY_SM-PD3S140-7,60V,N/A,E017965,POWERDI323-POWERDI323';
 PARENT_PPT_PHYS_PART = 'DIOSCHOTTKY_SM-PD3S140-7,60V,N/A,E017965,POWERDI323';
 PARENT_PPT = 'DIOSCHOTTKY';
 PARENT_PPT_PART = 'DIOSCHOTTKY_SM-PD3S140-7,60V,N/A,E017965,POWERDI323';
 PARENT_CHIPS_PHYS_PART = 'DIOSCHOTTKY_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I199@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C8';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I202@INDUCTORS.IND(CHIPS)';
LOCATION   = 'L4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ind/chips/chips.prt';
 PART_NAME = 'IND_SM-180NH,20,E026052,LSMSQ79H41-LSMSQ79H41';
 LONG_PART_NAME = 'IND_SM-180NH,20,E026052,LSMSQ79H41-LSMSQ79H41';
 PARENT_PPT_PHYS_PART = 'IND_SM-180NH,20,E026052,LSMSQ79H41';
 PARENT_PPT = 'IND';
 PARENT_PPT_PART = 'IND_SM-180NH,20,E026052,LSMSQ79H41';
 PARENT_CHIPS_PHYS_PART = 'IND_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I203@RESISTORS.RES(CHIPS)';
LOCATION   = 'R9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-2,E022716,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-2,E022716,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-2,E022716,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-2,E022716,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I208@RESISTORS.RES(CHIPS)';
LOCATION   = 'R10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-90.9K,E019943,1/10W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-90.9K,E019943,1/10W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-90.9K,E019943,1/10W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-90.9K,E019943,1/10W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I212@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C211';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I215@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C210';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I217@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C209';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I218@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I219@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E15';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I220@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E16';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I221@IC_ADI.ADP7182_V2(CHIPS)';
LOCATION   = 'U13';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/adp7182_v2/chips/chips.prt';
 PART_NAME = 'ADP7182_V2_SM-ADP7182ACPZ-R7,E017567,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'ADP7182_V2_SM-ADP7182ACPZ-R7,E017567,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'ADP7182_V2_SM-ADP7182ACPZ-R7,E017567,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'ADP7182_V2';
 PARENT_PPT_PART = 'ADP7182_V2_SM-ADP7182ACPZ-R7,E017567,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'ADP7182_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I223@RESISTORS.RES(CHIPS)';
LOCATION   = 'R1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-23.2K,E019517,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-23.2K,E019517,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-23.2K,E019517,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-23.2K,E019517,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I224@RESISTORS.RES(CHIPS)';
LOCATION   = 'R7';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-10.7K,E019637,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-10.7K,E019637,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-10.7K,E019637,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-10.7K,E019637,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I225@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C9';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 LONG_PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I226@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C10';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 LONG_PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I227@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C11';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 LONG_PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I228@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C12';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 LONG_PART_NAME = 'CAP_SM-47UF,10V,20,E020003,C1206H71-C1206H71';
 PARENT_PPT_PHYS_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-47UF,10V,20,E020003,C1206H71';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I230@IC_LIN.LINLT1964_5(CHIPS)';
LOCATION   = 'VR1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_lin/linlt1964_5/chips/chips.prt';
 PART_NAME = 'LINLT1964_5_SM-LT1964ES5-5#TRPBF,E013330,TSOT-5-TSOT-5';
 LONG_PART_NAME = 'LINLT1964_5_SM-LT1964ES5-5#TRPBF,E013330,TSOT-5-TSOT-5';
 PARENT_PPT_PHYS_PART = 'LINLT1964_5_SM-LT1964ES5-5#TRPBF,E013330,TSOT-5';
 PARENT_PPT = 'LINLT1964_5';
 PARENT_PPT_PART = 'LINLT1964_5_SM-LT1964ES5-5#TRPBF,E013330,TSOT-5';
 PARENT_CHIPS_PHYS_PART = 'LINLT1964_5_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I231@INDUCTORS.FERRITE(CHIPS)';
LOCATION   = 'E5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/inductors/ferrite/chips/chips.prt';
 PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 LONG_PART_NAME = 'FERRITE_SM-220OHM,25,E016865,L0402-L0402';
 PARENT_PPT_PHYS_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_PPT = 'FERRITE';
 PARENT_PPT_PART = 'FERRITE_SM-220OHM,25,E016865,L0402';
 PARENT_CHIPS_PHYS_PART = 'FERRITE_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I232@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C327';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I233@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C329';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I236@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C328';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE16_I238@RESISTORS.RES(CHIPS)';
LOCATION   = 'R154';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_COMP';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_COMP';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_COMP';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_FB';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_FB';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_FB';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SLEW';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SLEW';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_SLEW';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SS';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SS';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_SS';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SW';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_SW';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_SW';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_VREF';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_VREF';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_VREF';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_VREG';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP5074_I189_VREG';
PHY_SIGNAL = 'UNNAMED_16_ADP5074_I189_VREG';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I180_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I180_N1';
PHY_SIGNAL = 'UNNAMED_16_CAP_I180_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I199_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I199_N1';
PHY_SIGNAL = 'UNNAMED_16_CAP_I199_N1';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP7182V2_I221_ADJ';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP7182V2_I221_ADJ';
PHY_SIGNAL = 'UNNAMED_16_ADP7182V2_I221_ADJ';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP7182V2_I221_VOUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_ADP7182V2_I221_VOUT';
PHY_SIGNAL = 'UNNAMED_16_ADP7182V2_I221_VOUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I236_N1';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_16_CAP_I236_N1';
PHY_SIGNAL = 'UNNAMED_16_CAP_I236_N1';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

{--------------------------------------------------------------------------}

BEGIN_MODULE: '02_042233D_TOP' = '@02_042233D_LIB.02_042233D_TOP(SCH_1)';
PAGE = '35';

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I10@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C315';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
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END_LIB_INFO;
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
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BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I132@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C47';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I133@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C216';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.1UF,16V,20,E017331,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.1UF,16V,20,E017331,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I134@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C133';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I135@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C14';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I136@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C24';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-4.7UF,10V,10,E022491,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-4.7UF,10V,10,E022491,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I159@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A11';
SEC = '3';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I160@IC_ADI.AD8657_V2(CHIPS)';
LOCATION   = 'A11';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/ic_adi/ad8657_v2/chips/chips.prt';
 PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 LONG_PART_NAME = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7-QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT_PHYS_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_PPT = 'AD8657_V2';
 PARENT_PPT_PART = 'AD8657_V2_SM-AD8657ACPZ,E019277,QFN8_3X3_PAD2_44X1_7';
 PARENT_CHIPS_PHYS_PART = 'AD8657_V2_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I162@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C298';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I163@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C309';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 LONG_PART_NAME = 'CAP_SM-0.01UF,25V,10,E022720,C0201-(),C0201';
 PARENT_PPT_PHYS_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-0.01UF,25V,10,E022720,C0201';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I167@RESISTORS.RES(CHIPS)';
LOCATION   = 'R129';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I168@TRANSISTORS.TRANIRLMLXXXX(CHIPS)';
LOCATION   = 'Q4';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/tranirlmlxxxx/chips/chips.prt';
 PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 LONG_PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 PARENT_PPT_PHYS_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_PPT = 'TRANIRLMLXXXX';
 PARENT_PPT_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_CHIPS_PHYS_PART = 'TRANIRLMLXXXX_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I169@RESISTORS.RES(CHIPS)';
LOCATION   = 'R147';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 LONG_PART_NAME = 'RES_SM-20K,E003791,1/16W,1,R0402-R0402,R0402L_ALT';
 PARENT_PPT_PHYS_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-20K,E003791,1/16W,1,R0402';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I170@TRANSISTORS.TRANIRLMLXXXX(CHIPS)';
LOCATION   = 'Q5';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/transistors/tranirlmlxxxx/chips/chips.prt';
 PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 LONG_PART_NAME = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3-SOT23-M3';
 PARENT_PPT_PHYS_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_PPT = 'TRANIRLMLXXXX';
 PARENT_PPT_PART = 'TRANIRLMLXXXX_SM-IRLML5103TRPBF,E010204,SOT23-M3';
 PARENT_CHIPS_PHYS_PART = 'TRANIRLMLXXXX_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I172@DIODES.DIOZNR(CHIPS)';
LOCATION   = 'D26';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioznr/chips/chips.prt';
 PART_NAME = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA-DO214AA';
 LONG_PART_NAME = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA-DO214AA';
 PARENT_PPT_PHYS_PART = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA';
 PARENT_PPT = 'DIOZNR';
 PARENT_PPT_PART = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA';
 PARENT_CHIPS_PHYS_PART = 'DIOZNR_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I173@DIODES.DIOZNR(CHIPS)';
LOCATION   = 'D1';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/diodes/dioznr/chips/chips.prt';
 PART_NAME = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA-DO214AA';
 LONG_PART_NAME = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA-DO214AA';
 PARENT_PPT_PHYS_PART = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA';
 PARENT_PPT = 'DIOZNR';
 PARENT_PPT_PART = 'DIOZNR_SM-SMBJ5340B-TP,6V,5,E029884,DO214AA';
 PARENT_CHIPS_PHYS_PART = 'DIOZNR_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I176@RESISTORS.RES(CHIPS)';
LOCATION   = 'R162';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7,E004023,1/8W,5,R0805-R0805';
 LONG_PART_NAME = 'RES_SM-4.7,E004023,1/8W,5,R0805-R0805';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7,E004023,1/8W,5,R0805';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7,E004023,1/8W,5,R0805';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I177@RESISTORS.RES(CHIPS)';
LOCATION   = 'R163';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/resistors/res/chips/chips.prt';
 PART_NAME = 'RES_SM-4.7,E004023,1/8W,5,R0805-R0805';
 LONG_PART_NAME = 'RES_SM-4.7,E004023,1/8W,5,R0805-R0805';
 PARENT_PPT_PHYS_PART = 'RES_SM-4.7,E004023,1/8W,5,R0805';
 PARENT_PPT = 'RES';
 PARENT_PPT_PART = 'RES_SM-4.7,E004023,1/8W,5,R0805';
 PARENT_CHIPS_PHYS_PART = 'RES_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I178@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C175';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_PRIM:
PATH_NAME  = '@02_042233D_LIB.02_042233D_TOP(SCH_1):PAGE35_I180@CAPACITORS.CAP(CHIPS)';
LOCATION   = 'C179';
SEC = '1';

BEGIN_LIB_INFO:
 PRIM_FILE = 'Z:/allegro/v172_site/logical/share/library/capacitors/cap/chips/chips.prt';
 PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 LONG_PART_NAME = 'CAP_SM-1UF,16V,20,E020695,C0402-C0402,C0402L_ALT';
 PARENT_PPT_PHYS_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_PPT = 'CAP';
 PARENT_PPT_PART = 'CAP_SM-1UF,16V,20,E020695,C0402';
 PARENT_CHIPS_PHYS_PART = 'CAP_SM';
END_LIB_INFO;
END_PRIM;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I114_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I114_';
PHY_SIGNAL = 'UNNAMED_35_ADA48051_I114_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I114_VOUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I114_VOUT';
PHY_SIGNAL = 'UNNAMED_35_ADA48051_I114_VOUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I125_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I125_';
PHY_SIGNAL = 'UNNAMED_35_ADA48051_I125_';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I125_VOUT';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_ADA48051_I125_VOUT';
PHY_SIGNAL = 'UNNAMED_35_ADA48051_I125_VOUT';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_CAP_I76_N2';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_CAP_I76_N2';
PHY_SIGNAL = 'UNNAMED_35_CAP_I76_N2';
END_SIGNAL;

BEGIN_SIGNAL:
CANON_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_AD8657V2_I160_';
LOG_SIGNAL = '@02_042233D_LIB.02_042233D_TOP(SCH_1):UNNAMED_35_AD8657V2_I160_';
PHY_SIGNAL = 'UNNAMED_35_AD8657V2_I160_';
END_SIGNAL;

END_MODULE; { end of module '@02_042233D_LIB.02_042233D_TOP(SCH_1)'}

BEGIN_REFDES_LIST:
D12, Q6, R72, R625, C187, TP21, TDO, D13, R110, Q7, C188, C579, R73, C1, TP22, ~
D14, R111, C330, Q8, C189, R627, R74, C2, TP23, D15, R112, C331, Q9, R628, R75, ~
C3, TP24, D16, R113, C332, R76, C4, R791, R629, TP25, D17, R114, C333, C5, R77, ~
TP26, D18, C334, R115, C600, R78, C6, TP27, D19, C335, R116, R79, C7, C210, TP28, ~
R117, C211, C8, TP29, C336, R118, C212, C9, C337, R119, C213, R797, C338, C214, ~
R798, C339, C215, C216, C607, R160, C217, R161, C218, C40, C219, R162, C41, R163, ~
C42, R164, C774, DS11, C43, R165, C650, DS12, C44, C260, R166, C776, C651, D739, ~
C45, R167, C261, C652, C46, R168, C262, C47, R169, C263, C654, C48, C264, C655, ~
C49, C140, C265, C656, C141, C266, C657, C142, C267, C658, U777, C143, C268, C~
659, U778, IO3, C90, C144, C269, C801, C91, R30, C145, C92, R31, C146, C803, RT1, ~
C93, R32, C147, RT2, R33, C148, C94, C805, RT3, R34, C149, C95, VIN, RT4, R35, ~
C96, R750, C807, RT5, R36, C97, RT6, C98, R37, R752, RT7, R38, C190, C99, RT8, ~
R39, C191, RT9, C192, R630, R1, R631, C193, R2, R3, L759, R632, C194, D20, R80, ~
R4, C195, D21, R81, R5, R634, C196, TP30, D22, R82, R6, C588, R635, DS1, C197, ~
TP31, D23, R120, R83, D1, C198, DS2, C589, R636, E677, R7, D2, R121, R84, C199, ~
D24, R8, DS3, C340, D3, R122, R85, R638, D25, R9, D4, R123, R86, D26, D5, R124, ~
R87, D27, D6, R125, R88, D28, D7, R126, C220, R517, R89, D29, D8, R127, C737, ~
C221, W1, D9, R128, C738, R681, C222, W2, R129, C614, C223, W3, C224, C615, W4, ~
C100, C225, C616, D741, W5, C226, C617, R685, C101, W6, R170, C102, C227, C618, ~
W7, R171, C103, C228, Y523, C781, W8, C50, R172, C104, C229, C782, W9, C51, R173, ~
C105, R689, R174, C106, C52, C53, R175, C107, C660, C54, R176, C108, C270, C55, ~
R177, C109, C271, C662, C787, R178, C272, C56, C788, C663, RT10, C57, R179, C273, ~
C789, C664, U783, 1V35, RT11, C58, C274, C665, RT12, C59, C150, C275, C666, RT13, ~
C151, A10, C276, C667, RT14, C152, C277, C668, A11, RT15, C153, R200, C669, C278, ~
A12, RT16, C154, R201, A13, C279, RT17, R40, C155, R202, A14, RT18, R41, C156, ~
A15, R203, R42, C157, R204, R43, C158, Y578, R205, R44, C159, C300, R206, U10, ~
RX, R45, C301, U11, R760, R207, R46, C302, R208, U12, R47, C303, Q512, U13, R209, ~
GND_10, R48, C304, U14, R763, R49, C305, R764, U15, C306, R765, R640, U16, S1, ~
TP1, C307, R766, E682, L10, U17, TP2, U18, C308, C595, R642, TP3, U19, C309, L~
520, C596, R90, D30, VCCPINT, TP4, L13, L521, C597, R91, TP5, L14, C598, R92, ~
-3V3_A, TP6, R93, R130, L15, E1, C740, C599, E687, TP7, E2, R94, R131, L16, E3, ~
R95, R132, C742, C10, TP8, E4, R96, R133, C11, TP9, E5, R97, R134, C12, E6, R98, ~
R135, C745, C13, R99, R136, C230, C14, E7, C746, R137, C231, E8, C15, R138, C232, ~
E9, C748, R691, C16, R139, C233, C17, C234, C18, W10, C110, C235, C19, C626, W11, ~
C111, C236, W12, R180, C112, C237, C790, W13, R181, C113, C238, W14, C60, R182, ~
C114, C239, C792, W15, C61, R183, C115, C793, W16, C62, R184, C116, W17, C63, ~
R185, C117, C795, R576, C670, C64, R186, C118, R577, C671, C280, C65, R187, C119, ~
C672, C281, C66, R188, C673, C282, C67, R189, C674, C283, C68, C284, C675, C69, ~
C160, C285, E10, U508, C676, P510, DS690, C161, C286, U509, E11, C162, C287, E12, ~
C678, C163, C288, E767, R601, C679, E13, R210, C164, C289, E14, E768, R602, R211, ~
C165, R50, R603, E15, R212, C166, R51, R604, P516, E16, R213, C167, R52, E17, ~
R605, R214, A1, C168, R53, E18, R606, C700, R215, A2, C169, R54, U20, C310, P519, ~
C701, E19, R216, A3, R55, C311, U21, R608, R770, C702, R217, A4, R56, U22, C312, ~
R609, R771, C703, R218, A5, R57, C313, U23, R772, Q522, C704, R219, R58, A6, C~
314, R773, C705, R59, A7, C315, C706, CALIB_REF1, A8, C316, R775, C707, CALIB_~
REF2, A9, C317, C708, C318, C709, C319, R653, R779, R140, F1, R141, C751, F2, ~
C20, R142, F3, C21, R143, C753, R800, F4, C22, R144, C754, F5, R145, C755, C23, ~
6V0_A, C24, R146, C756, C240, C25, Y1, R147, C757, C241, C26, C242, R148, C758, ~
C633, C27, C243, R149, C28, C244, -6V0_A, C29, C120, C245, C121, C246, R580, C~
637, C122, R190, C247, R581, 3V3_A, C123, R191, C248, R582, C639, C70, C124, R~
192, C249, R583, C71, C125, R193, R584, R10, 3V3_D, 1V8_A, C72, C126, R194, U511, ~
R585, R11, C73, C127, R195, R586, C680, R12, R13, C74, C128, R196, C290, R587, ~
1V8_D, R14, C75, C129, R197, C291, R15, C76, R198, C292, C683, R16, C77, R199, ~
C293, C684, R17, C78, C294, R18, C79, C170, C295, E20, U518, C686, R19, C171, ~
C296, E21, P1, C172, C297, R610, C688, E22, C173, C298, R611, E23, TCK, R220, ~
C174, C299, R612, E24, R221, R60, E25, C175, R613, R61, TP10, E26, C176, R62, ~
TP11, C177, E27, R63, R100, C710, C178, TP12, R64, R101, C320, C179, C711, TP13, ~
TX, GND_4, R65, R102, C321, R780, C712, TP14, GND_5, OFF_SC1, R66, R103, C322, ~
R619, C713, TP15, GND_6, OFF_SC2, R104, C323, R67, TP16, GND_7, R105, C324, R68, ~
TP17, GND_8, R106, C325, C200, R784, R69, TP18, GND_9, R107, C326, U1, C201, T~
P19, U2, R108, C327, C202, R661, R109, U3, C203, C328, U4, C204, C329, C205, U5, ~
C206, U6, R150, U7, C207, U8, R151, C761, C208, C30, U9, R152, C762, C209, C31, ~
R153, C32, R154, C33, R155, C34, C250, R156, C641, C35, C251, R157, C36, C252, ~
R158, C643, C37, C253, R159, C769, C644, C38, C254, C645, C39, C130, C255, C131, ~
C256, R590, C647, C132, C257, R591, C648, L1, C258, C133, R592, C649, L2, 4V0_A, ~
C80, C134, C259, L3, R593, R20, C81, C135, R594, L4, TMS, R21, C82, C136, L5, ~
U646, VR1, R22, C83, C137, L6, VR2, R23, C84, C138, L7, C85, R24, C139, U524, ~
C692, L8, C86, R25, L9, C87, R26, C88, R27, C89, R28, C180, R743, C696, R29, C~
181, R744, C697, TDI, Q1, R620, E786, C698, C182, Q2, R621, C699, C183, Q3, C184, ~
R747, R622, D10, Q4, R70, C185, R623, Q785, D11, R71, C186, Q5, R624, R749, TP20;
END_REFDES_LIST; { end of REFDES_LIST }
