| Device Utilization Summary (actual values) | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
9,241 |
407,600 |
2% |
|
| Number used as Flip Flops |
9,189 |
|
|
|
| Number used as Latches |
0 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
52 |
|
|
|
| Number of Slice LUTs |
10,100 |
203,800 |
4% |
|
| Number used as logic |
8,610 |
203,800 |
4% |
|
| Number using O6 output only |
6,335 |
|
|
|
| Number using O5 output only |
207 |
|
|
|
| Number using O5 and O6 |
2,068 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
1,155 |
64,000 |
1% |
|
| Number used as Dual Port RAM |
620 |
|
|
|
| Number using O6 output only |
160 |
|
|
|
| Number using O5 output only |
14 |
|
|
|
| Number using O5 and O6 |
446 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
535 |
|
|
|
| Number using O6 output only |
533 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
1 |
|
|
|
| Number used exclusively as route-thrus |
335 |
|
|
|
| Number with same-slice register load |
303 |
|
|
|
| Number with same-slice carry load |
32 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
4,684 |
50,950 |
9% |
|
| Number of LUT Flip Flop pairs used |
12,853 |
|
|
|
| Number with an unused Flip Flop |
4,465 |
12,853 |
34% |
|
| Number with an unused LUT |
2,753 |
12,853 |
21% |
|
| Number of fully used LUT-FF pairs |
5,635 |
12,853 |
43% |
|
| Number of unique control sets |
563 |
|
|
|
Number of slice register sites lost
to control set restrictions |
2,241 |
407,600 |
1% |
|
| Number of bonded IOBs |
64 |
500 |
12% |
|
| Number of LOCed IOBs |
64 |
64 |
100% |
|
| IOB Flip Flops |
24 |
|
|
|
| IOB Master Pads |
2 |
|
|
|
| IOB Slave Pads |
2 |
|
|
|
| Number of RAMB36E1/FIFO36E1s |
16 |
445 |
3% |
|
| Number using RAMB36E1 only |
16 |
|
|
|
| Number using FIFO36E1 only |
0 |
|
|
|
| Number of RAMB18E1/FIFO18E1s |
0 |
890 |
0% |
|
| Number of BUFG/BUFGCTRLs |
3 |
32 |
9% |
|
| Number used as BUFGs |
3 |
|
|
|
| Number used as BUFGCTRLs |
0 |
|
|
|
| Number of IDELAYE2/IDELAYE2_FINEDELAYs |
8 |
500 |
1% |
|
| Number used as IDELAYE2s |
8 |
|
|
|
| Number used as IDELAYE2_FINEDELAYs |
0 |
|
|
|
| Number of ILOGICE2/ILOGICE3/ISERDESE2s |
25 |
500 |
5% |
|
| Number used as ILOGICE2s |
17 |
|
|
|
| Number used as ILOGICE3s |
0 |
|
|
|
| Number used as ISERDESE2s |
8 |
|
|
|
| Number of ODELAYE2/ODELAYE2_FINEDELAYs |
0 |
150 |
0% |
|
| Number of OLOGICE2/OLOGICE3/OSERDESE2s |
39 |
500 |
7% |
|
| Number used as OLOGICE2s |
6 |
|
|
|
| Number used as OLOGICE3s |
0 |
|
|
|
| Number used as OSERDESE2s |
33 |
|
|
|
| Number of PHASER_IN/PHASER_IN_PHYs |
1 |
40 |
2% |
|
| Number used as PHASER_INs |
0 |
|
|
|
| Number used as PHASER_IN_PHYs |
1 |
|
|
|
| Number of LOCed PHASER_IN_PHYs |
1 |
1 |
100% |
|
| Number of PHASER_OUT/PHASER_OUT_PHYs |
4 |
40 |
10% |
|
| Number used as PHASER_OUTs |
0 |
|
|
|
| Number used as PHASER_OUT_PHYs |
4 |
|
|
|
| Number of LOCed PHASER_OUT_PHYs |
4 |
4 |
100% |
|
| Number of BSCANs |
1 |
4 |
25% |
|
| Number of BUFHCEs |
0 |
168 |
0% |
|
| Number of BUFRs |
0 |
40 |
0% |
|
| Number of CAPTUREs |
0 |
1 |
0% |
|
| Number of DNA_PORTs |
0 |
1 |
0% |
|
| Number of DSP48E1s |
3 |
840 |
1% |
|
| Number of EFUSE_USRs |
0 |
1 |
0% |
|
| Number of FRAME_ECCs |
0 |
1 |
0% |
|
| Number of GTXE2_CHANNELs |
0 |
16 |
0% |
|
| Number of GTXE2_COMMONs |
0 |
4 |
0% |
|
| Number of IBUFDS_GTE2s |
0 |
8 |
0% |
|
| Number of ICAPs |
0 |
2 |
0% |
|
| Number of IDELAYCTRLs |
1 |
10 |
10% |
|
| Number of IN_FIFOs |
1 |
40 |
2% |
|
| Number of LOCed IN_FIFOs |
1 |
1 |
100% |
|
| Number of MMCME2_ADVs |
1 |
10 |
10% |
|
| Number of LOCed MMCME2_ADVs |
1 |
1 |
100% |
|
| Number of OUT_FIFOs |
4 |
40 |
10% |
|
| Number of LOCed OUT_FIFOs |
4 |
4 |
100% |
|
| Number of PCIE_2_1s |
0 |
1 |
0% |
|
| Number of PHASER_REFs |
2 |
10 |
20% |
|
| Number of LOCed PHASER_REFs |
2 |
2 |
100% |
|
| Number of PHY_CONTROLs |
2 |
10 |
20% |
|
| Number of LOCed PHY_CONTROLs |
2 |
2 |
100% |
|
| Number of PLLE2_ADVs |
1 |
10 |
10% |
|
| Number of LOCed PLLE2_ADVs |
1 |
1 |
100% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of XADCs |
1 |
1 |
100% |
|
| Average Fanout of Non-Clock Nets |
3.63 |
|
|
|