uC | uC
1.0 |
2012.08.14.17:02:38 | Generation Report |
Output Directory | D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/ | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Files | D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/uC.v (614711 bytes VERILOG)
D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_pll.v (10361 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_onchip_mem.hex (21517 bytes HEX) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_onchip_mem.v (3881 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_leds.v (2132 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_ucprobe_uart.v (23501 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_ucprobe_uart_input_mutex.dat (3 bytes OTHER) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_ucprobe_uart_input_stream.dat (10 bytes OTHER) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_ucprobe_uart_output_stream.dat (0 bytes OTHER) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_sys_timer.v (6878 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_mm_console_master.v (15640 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_jtag_interface.v (2357 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_jtag_dc_streaming.v (7339 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_jtag_sld_node.v (5844 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_jtag_streaming.v (23657 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_pli_streaming.v (2285 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_idle_remover.v (1891 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_idle_inserter.v (2037 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_jtag_interface.sdc (140 bytes SDC) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_mm_console_master_timing_adt.v (1795 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_bytes_to_packets.v (4919 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_packets_to_bytes.v (7863 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_packets_to_master.v (51852 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_mm_console_master_b2p_adapter.v (1522 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_mm_console_master_p2b_adapter.v (1358 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_pwr_data.v (3324 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_i2c_int.v (2358 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_pwr_en_clk.v (2197 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu.sdc (3407 bytes SDC) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu.v (190093 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_jtag_debug_module_sysclk.v (6895 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_jtag_debug_module_tck.v (8109 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_jtag_debug_module_wrapper.v (9839 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_ociram_default_contents.mif (5878 bytes MIF) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_oci_test_bench.v (1426 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_rf_ram_a.mif (600 bytes MIF) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_rf_ram_b.mif (600 bytes MIF) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cpu_test_bench.v (29784 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_sysid.v (1441 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_tri_state_bridge_0_bridge_0.sv (5451 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_tri_state_bridge_0_pinSharer_0.v (4701 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_tri_state_bridge_0_pinSharer_0_pin_sharer.sv (4027 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_std_arbitrator_core.sv (8985 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_tri_state_bridge_0_pinSharer_0_arbiter.sv (2863 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_sram.v (28074 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_tristate_controller_translator.sv (7075 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_slave_translator.sv (15976 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_tristate_controller_aggregator.sv (9358 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/write_master.v (5448 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/Eval_Board_interface.v (15606 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/AD7689_Avalon_core.v (20599 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_master_translator.sv (16415 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_master_agent.sv (8662 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_slave_agent.sv (17560 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10392 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_addr_router.sv (6577 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_addr_router_001.sv (9189 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_addr_router_002.sv (6334 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_addr_router_003.sv (5989 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_id_router.sv (5883 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_id_router_001.sv (5978 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_id_router_002.sv (6063 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_id_router_003.sv (5814 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_burst_adapter.sv (36989 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_demux.sv (4743 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_demux_001.sv (11168 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_demux_002.sv (4114 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_demux_003.sv (3477 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_mux.sv (12236 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_mux_001.sv (13093 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_cmd_xbar_mux_002.sv (13942 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_demux.sv (4098 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_demux_001.sv (4740 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_demux_002.sv (5374 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_demux_003.sv (3472 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_mux.sv (13051 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_mux_001.sv (21635 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_rsp_xbar_mux_002.sv (12210 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_merlin_width_adapter.sv (36187 bytes SYSTEM_VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG) D:/AD/AnalogSVN/CED1Z/AD7689/NiosCpu/uC/synthesis/submodules/uC_irq_mapper.sv (1903 bytes SYSTEM_VERILOG) |
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Instantiations |
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