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====== ADAU1373 Sound CODEC Linux Driver ======


===== Supported Devices =====

  * [[adi>ADAU1373]]

===== Evaluation Boards =====
  * [[adi>EVAL-ADAU1373Z]]

===== Source Code =====

==== Status ====

^ Source ^ Mainlined? ^
| [[git.linux.org>sound/soc/codecs/adau1373.c|git]] | [[git.linux.org>sound/soc/codecs/adau1373.c|Yes]] |

==== Files ====

^ Function ^ File ^
| driver  | [[git.linux.org>sound/soc/codecs/adau1373.c]] |
| include | [[git.linux.org>sound/soc/codecs/adau1373.h]] |
| include | [[git.linux.org>include/sound/adau1373.h]] |

===== Example device initialization =====

{{page>software/linux/docs/platform_and_bus_model#Platform Data&noheader&firstseconly&noeditbtn}}

==== I2C ====

{{page>software/linux/docs/platform_and_bus_model#Declaring I2C devices&firstseconly&noeditbtn}}

<code c>
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {

	[--snip--]
	{
		I2C_BOARD_INFO("adau1373", 0x1a),
	},
	[--snip--]
}

</code>

<code c>
static int __init stamp_init(void)
{
	[--snip--]
	i2c_register_board_info(0, bfin_i2c_board_info,
				ARRAY_SIZE(bfin_i2c_board_info));
	[--snip--]

	return 0;
}
arch_initcall(board_init);
</code>

===== ASoC DAPM Widgets =====

^ Name ^ Description ^
| AIN1L | Left Channel Input 1 |
| AIN1R | Right Channel Input 1 |
| AIN2L | Left Channel Input 2 |
| AIN2R | Right Channel Input 2 |
| AIN3L | Left Channel Input 3 |
| AIN3R | Right Channel Input 3 |
| AIN4L | Left Channel Input 4 |
| AIN4R | Right Channel Input 4 |
| DMIC1DAT | Serial Data Input Digital Microphone 1 and 2 |
| DMIC2DAT | Serial Data Input Digital Microphone 3 and 4 |
| LOUT1L | Left Channel Line Output 1 |
| LOUT1R | Right Channel Line Output 1 |
| LOUT2L | Left Channel Line Output 2 |
| LOUT2R | Right Channel Line Output 2 |
| HPL | Left Headphone Output |
| HPR | Right Headphone Output |
| SPKL | Left Speaker Output |
| SPKR | Right Speaker Output |
| EP | Eearpiece Output |
| MICBIAS1 | Micbias 1 supply |
| MICBIAS2 | Micbias 2 supply |

===== ALSA Controls =====

^ Name ^ Description ^ Configuration ^
| AIF1 Capture Volume | Digital Audio Interface A Recording Volume | |
| AIF2 Capture Volume | Digital Audio Interface B Recording Volume | |
| AIF3 Capture Volume | Digital Audio Interface C Recording Volume | |
| ADC Capture Volume | ADC Recording Volume | |
| DMIC Capture Volume | DMIC Recording Volume | |
| Input 1 Capture Volume | Input 1 Gain | |
| Input 2 Capture Volume | Input 2 Gain | |
| Input 3 Capture Volume | Input 3 Gain | |
| Input 4 Capture Volume | Input 4 Gain | |
| Input 1 Boost Capture Volume | Input 1 ADC Boost (+20dB) | |
| Input 2 Boost Capture Volume | Input 2 ADC Boost (+20dB) | |
| Input 3 Boost Capture Volume | Input 3 ADC Boost (+20dB) | |
| Input 4 Boost Capture Volume | Input 4 ADC Boost (+20dB) | |
| AIF1 Playback Volume | Digital Audio Interface A Playback Datapath Volume | |
| AIF2 Playback Volume | Digital Audio Interface B Playback Datapath Volume | |
| AIF3 Playback Volume | Digital Audio Interface C Playback Datapath Volume | |
| DAC1 Playback Volume | DAC1 Playback Volume | |
| DAC2 Playback Volume | DAC2 Playback Volume | |
| Lineout1 Playback Volume | Lineout 1 Volume | |
| Lineout2 Playback Volume | Lineout 2 Volume | Single-ended lineout |
| Speaker Playback Volume  | Speaker Out Volume | |
| Headphone Playback Volume | Heaphone Out Volume| |
| Earpiece Playback Volume | Earpiece Amplifier Gain | |
| AIF1 Boost Playback Volume | Digital Audio Interface A Playback Gain (+6dB) | |
| AIF2 Boost Playback Volume | Digital Audio Interface B Playback Gain (+6dB) | |
| AIF3 Boost Playback Volume | Digital Audio Interface C Playback Gain (+6dB) | |
| AIF1 Boost Capture Volume | Digital Audio Interface C Recording Gain (+6dB) | |
| AIF2 Boost Capture Volume | Digital Audio Interface C Recording Gain (+6dB) | |
| AIF3 Boost Capture Volume | Digital Audio Interface C Recording Gain (+6dB) | |
| ADC Boost Capture Volume | ADC Recording Gain (+6dB) | |
| DMIC Boost Capture Volume | DMIC Recording Gain (+6dB) | |
| DAC1 Boost Playback Volume | DAC1 Playback Gain (+6dB) | |
| DAC2 Boost Playback Volume | DAC1 Playback Gain (+6dB) | |
| Speaker Boost Playback Volume | Speaker Output Gain  | |
| Lineout1 LR Mux | Lineout1 Left-Right Mux (Mono Stereo Control)\\ Valid values: "Mute", "Right Channel (L+R)", "Left Channel (L+R)", "Stereo" | |
| Lineout2 LR Mux  | Lineout2 Left-Right Mux (Mono Stereo Control)\\ Valid values: "Mute", "Right Channel (L+R)", "Left Channel (L+R)", "Stereo" | Single-ended lineout |
| Speaker LR Mux | Speaker Left-Right Mux (Mono Stereo Control)\\ Valid values: "Mute", "Right Channel (L+R)", "Left Channel (L+R)", "Stereo" | |
| HPF Cutoff | High-pass-filter cutoff frequency.\\ Valid values: "3.7Hz", "50Hz", "100Hz", ... steps of 50Hz ..., "800Hz" | |
| HPF Switch | Enable/Disable High-pass-filter | |
| HPF Channel | Hight-pass-filter channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5" | |
| Bass HPF Cutoff | Bass High-pass-filter cutoff frequency.\\ Valid values:  "158Hz", "232Hz", "347Hz", "520Hz" | |
| Bass Clip Level Threshold | Signal Extend Density (Clip Level). Overdrive level for bass enhancement. \\ Valid values: "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875" | |
| Bass LPF Cutoff | Bass Low-pass-filter cutoff frequency.\\ Valid values: "801Hz", "1001Hz" | |
| Bass Playback Switch | Enable/Disable Bass Enhancement | |
| Bass Playback Volume | Bass Enhancement Gain | |
| Bass Channel | Bass Enhancement Channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5"  | |
| 3D Freq | 3D Enhancement cutoff frequency (relative to the sampling rate).\\ Valid values: "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs", "0.16875 fs", "0.27083 fs" |
| 3D Level | 3D Enhancement effect level. \\ Valid values: "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%", "40%", "46.67%", "53.33%", \\ "60%", "66.67%", "73.33%", "80%", "86.67", "93.33%", "100%" | |
| 3D Playback Switch | Enable/Disable 3D Enhancement | |
| 3D Playback Volume | 3D Enhancement Gain | |
| 3D Channel | 3D Enhancement Channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5" | |
| Zero Cross Switch | Enable/Disable Zero-Cross-Detection for volume updates | |
| DRC1 Channel | Dynamic Range Control 1 Channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5" | |
| DRC2 Channel | Dynamic Range Control 2 Channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5" | |
| DRC3 Channel | Dynamic Range Control 3 Channel.\\ Valid values: "Channel1", "Channel2", "Channel3", "Channel4", "Channel5" | |

===== PLL Configuration ======

The ADAU1373 features two PLLs:

<code c>
enum adau1373_pll {
    ADAU1373_PLL1 = 0,
    ADAU1373_PLL2 = 1,
};
</code>

Each PLLs input frequency can be selected from a variety of signals: 
<code c>
enum adau1373_pll_src {
    ADAU1373_PLL_SRC_MCLK1 = 0,
    ADAU1373_PLL_SRC_BCLK1 = 1,
    ADAU1373_PLL_SRC_BCLK2 = 2,
    ADAU1373_PLL_SRC_BCLK3 = 3,
    ADAU1373_PLL_SRC_LRCLK1 = 4,
    ADAU1373_PLL_SRC_LRCLK2 = 5,
    ADAU1373_PLL_SRC_LRCLK3 = 6,
    ADAU1373_PLL_SRC_GPIO1 = 7,
    ADAU1373_PLL_SRC_GPIO2 = 8,
    ADAU1373_PLL_SRC_GPIO3 = 9,
    ADAU1373_PLL_SRC_GPIO4 = 10,
    ADAU1373_PLL_SRC_MCLK2 = 11,
};
</code>

The input frequency must configured to be between 7813 and 27000000 Hz. The output frequency must be configured to be between 45158000 and 49152000. Configuring the PLL with other input or output frequency will fail.

The PLL runs at 1024 times the base sample rate. So for a 48000 Hz based sample rate you'd normally choose 49152000 Hz for the PLL output frequncey and for a 44100 Hz based sample rate 45158400 Hz.

===== DAI configuration =====

The codec driver registers three DAIs:
  * "adau1373-aif1" (Digital Audio Interface A)
  * "adau1373-aif2" (Digital Audio Interface B)
  * "adau1373-aif3" (Digital Audio Interface C)

==== Supported DAI formats ====

^ Name ^ Supported by driver ^ Description ^
| SND_SOC_DAIFMT_I2S     | yes | I2S mode |
| SND_SOC_DAIFMT_RIGHT_J | yes | Right Justified mode |
| SND_SOC_DAIFMT_LEFT_J  | yes | Left Justified mode  |
| SND_SOC_DAIFMT_DSP_A   | no  | data MSB after FRM LRC |
| SND_SOC_DAIFMT_DSP_B   | yes | data MSB during FRM LRC  |
| SND_SOC_DAIFMT_AC97    | no  | AC97 mode |
| SND_SOC_DAIFMT_PDM     | no  | Pulse density modulation |
| | |
| SND_SOC_DAIFMT_NB_NF | yes  | Normal bit- and frameclock |
| SND_SOC_DAIFMT_NB_IF | yes | Normal bitclock, inverted frameclock |
| SND_SOC_DAIFMT_IB_NF | yes | Inverted frameclock, normal bitclock |
| SND_SOC_DAIFMT_IB_IF | yes | Inverted bit- and frameclock |
| | |
| SND_SOC_DAIFMT_CBM_CFM | yes | Codec bit- and frameclock master |
| SND_SOC_DAIFMT_CBS_CFM | no  | Codec bitclock slave, frameclock master |
| SND_SOC_DAIFMT_CBM_CFS | no  | Codec bitclock master, frameclock slave |
| SND_SOC_DAIFMT_CBS_CFS | yes | Codec bit- and frameclock slave |

==== DAI sysclk ====

The DAIs can either use PLL1 or PLL2 as source. When configuring a DAI its rate should be set to the rate of the source PLL.

<code c>
enum adau1373_clk_src {
    ADAU1373_CLK_SRC_PLL1 = 0,
    ADAU1373_CLK_SRC_PLL2 = 1,
};
</code>

==== Example DAI configuration ====

<code c>
static int bfin_eval_adau1373_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	int ret;
	int pll_rate;

	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;

	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
			SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
	if (ret)
		return ret;

	switch (params_rate(params)) {
	case 48000:
	case 8000:
	case 12000:
	case 16000:
	case 24000:
	case 32000:
		pll_rate = 48000 * 1024;
		break;
	case 44100:
	case 7350:
	case 11025:
	case 14700:
	case 22050:
	case 29400:
		pll_rate = 44100 * 1024;
		break;
	default:
		return -EINVAL;
	}

	ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
			ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
	if (ret)
		return ret;

	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
			SND_SOC_CLOCK_IN);

	return ret;
}

static int bfin_eval_adau1373_codec_init(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_soc_dai *codec_dai = rtd->codec_dai;
	unsigned int pll_rate = 48000 * 1024;
	int ret;

	ret = snd_soc_dai_set_pll(codec_dai, ADAU1373_PLL1,
			ADAU1373_PLL_SRC_MCLK1, 12288000, pll_rate);
	if (ret)
		return ret;

	ret = snd_soc_dai_set_sysclk(codec_dai, ADAU1373_CLK_SRC_PLL1, pll_rate,
			SND_SOC_CLOCK_IN);

	return ret;
}
static struct snd_soc_ops bfin_eval_adau1373_ops = {
	.hw_params = bfin_eval_adau1373_hw_params,
};

static struct snd_soc_dai_link bfin_eval_adau1373_dai = {
	.name = "adau1373",
	.stream_name = "adau1373",
	.cpu_dai_name = "bfin-i2s.0",
	.codec_dai_name = "adau1373-aif1",
	.platform_name = "bfin-i2s-pcm-audio",
	.codec_name = "adau1373.0-001a",
	.ops = &bfin_eval_adau1373_ops,
	.init = bfin_eval_adau1373_codec_init,
};
</code>

====== ADAU1373 evaluation board driver ======

There is no dedicated Blackfin STAMP evaluation board for the ADAU1373. During test and driver development we used the [[adi>EVAL-ADAU1373]] board.

It can be easily wired to the Blackfin STAMP SPORT header.

===== Source =====

==== Status ====

^  Source  ^  Mainlined?  ^
| [[git.linux.org>sound/soc/blackfin/bfin-eval-adau1373.c|git]] | [[git.linux.org>sound/soc/blackfin/bfin-eval-adau1373.c|yes]] |

==== Files ====

^ Function ^ File ^
| driver  | [[git.linux.org>sound/soc/blackfin/bfin-eval-adau1373.c]] |

===== Kernel configuration =====

<code>
Device Drivers  --->
[*] I2C support  --->
[*]   I2C Hardware Bus support  --->
***     I2C system bus drivers (mostly embedded / system-on-chip) ***
<*>       Blackfin TWI I2C support
(100)     Blackfin TWI I2C clock (kHz)
</code>

Enable ALSA SoC evaluation board driver:
<code>
Device Drivers  --->
<M> Sound card support  --->
<M>   Advanced Linux Sound Architecture  --->
<M>     ALSA for SoC audio support  --->
<M>       Support for the EVAL-ADAU1373 boards on Blackfin eval boards
</code>

===== Hardware configuration =====

Connect the STAMP SPORT 0 port (P6) to the EVAL-ADAU1373 J23 and J28 headers.

Note that the SPORT has separate signals for the capture and playback clocks, while the ADAU1373 uses the same clock signals for both, so the EVAL-ADU1373 clock signal pins need to be connected to two STAMP pins each.

^ STAMP pin ^ EVAL-ADAU1373 pin ^ Function ^
| P6-26 (SPORT 0 - PJ2_SCL) | J23-1 | I2C SCL |
| P6-24 (SPORT 0 - PJ3_SDA) | J23-3 | I2C SDA |
| P6-6  (SPORT 0 - PJ9_TSCLK0), P6-16 (SPORT 0 - PJ6_RSCLK0) | J28-6 (A_BCLK) | BCLK |
| P6-11 (SPORT 0 - PJ10_TFS0), P6-7 (SPORT 0 - PJ7_RFS0) | J28-8 (A_LRC) | LRCLK |
| P6-14 (SPORT 0 - PJ11_DT0PRI | J28-10 (A_DACDAT) | Playback data |
| P6-8  (SPORT 0 - PJ8_DR0PRI) | J28-12 (A_ADCDAT) | Captrue data |
| P6-33 | J28-1 | GND |


===== Driver testing =====

Load the driver and make sure the sound card is properly instantiated.

<WRAP box bggreen><wrap info>This specifies any shell prompt running on the target</wrap>
<xterm>
root:/> modprobe snd-bf5xx-i2s
root:/> modprobe snd-soc-bf5xx-i2s
root:/> modprobe snd-soc-adau1373
root:/> modprobe snd-soc-bfin-eval-adau1373
dma rx:3 tx:4, err irq:45, regs:ffc00800
asoc: ADAU1373 <-> bf5xx-i2s mapping ok
</xterm>
</WRAP>

<WRAP box bggreen><wrap info>This specifies any shell prompt running on the target</wrap>
<xterm>
root:/> modprobe snd-pcm-oss
root:/> tone
TONE: generating sine wave at 1000 Hz...

root:/> arecord -f cd | aplay
Recording WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Playing WAVE 'stdin' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
</xterm>
</WRAP>
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