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resources:tools-software:linux-drivers:iio-resolver:ad2s1210 [05 Dec 2023 22:32] – make the raw examples more readable Trevor Gamblin | resources:tools-software:linux-drivers:iio-resolver:ad2s1210 [07 Dec 2023 15:44] (current) – added setup images Trevor Gamblin | ||
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To configure the chip, use the attributes according to the device register to IIO ABI mapping below: | To configure the chip, use the attributes according to the device register to IIO ABI mapping below: | ||
- | ^ Register | + | ^ Register |
- | |DOS Overrange Threshold | + | |DOS Overrange Threshold |
- | |DOS Mismatch Threshold | + | |DOS Mismatch Threshold |
- | |DOS Reset Maximum Threshold | 0x8B | events/ | + | |DOS Reset Maximum Threshold | 0x8B | events/ |
- | |DOS Reset Minimum Threshold | 0x8C | events/ | + | |DOS Reset Minimum Threshold | 0x8C | events/ |
- | |LOT High Threshold | + | |LOT High Threshold |
- | |LOT Low Threshold | + | |LOT Low Threshold |
- | |Excitation Frequency | + | |Excitation Frequency |
- | |Control | + | |Control |
- | | Phase lock range | D5 | events/ | + | | Phase lock range | D5 | events/ |
- | | Hysteresis | + | | Hysteresis |
- | | Encoder resolution | + | | Encoder resolution |
- | | Resolution | + | | Resolution |
- | |Soft Reset | 0xF0 | [2] | | + | |Soft Reset | 0xF0 | | | Soft reset is performed when `out_altvoltage0_frequency` is written.| |
- | |Fault | + | |Fault |
- | [1]: The value written to the LOT low register is high value minus the | + | ===== Interfacing With the AD2S1210 via iio_attr |
- | hysteresis. | + | |
- | + | ||
- | [2]: Soft reset is performed when `out_altvoltage0_frequency` is written. | + | |
- | + | ||
- | ===== Reading Raw Data ===== | + | |
Accessing a list of channels: | Accessing a list of channels: | ||
Line 110: | Line 105: | ||
</ | </ | ||
- | For example, to get position channel **angl1**: | + | For example, to get position channel **angl0**: |
<WRAP box bggreen>< | <WRAP box bggreen>< | ||
< | < | ||
Line 131: | Line 126: | ||
</ | </ | ||
- | Alternatively, | + | ===== Interfacing With the AD2S1210 via /sys/bus ===== |
+ | |||
+ | Alternatively, | ||
<WRAP box bggreen>< | <WRAP box bggreen>< | ||
Line 137: | Line 134: | ||
analog@setup-2-zed: | analog@setup-2-zed: | ||
- | analog@setup-2-zed:/ | + | analog@setup-2-zed:/ |
- | total 0 | + | . |
- | drwxr-xr-x 2 root root 0 Dec 5 16:05 buffer | + | ├── |
- | drwxr-xr-x 2 root root 0 Dec 5 16:05 buffer0 | + | │ ├── data_available |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 current_timestamp_clock | + | │ ├── direction |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 dev | + | │ ├── enable |
- | drwxr-xr-x 2 root root 0 Dec 5 16:05 events | + | │ ├── length |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_altvoltage0_label | + | │ └── watermark |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_altvoltage1_label | + | ├── |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_altvoltage2_label | + | │ ├── data_available |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 in_angl0_hysteresis | + | │ ├── direction |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_angl0_hysteresis_available | + | │ ├── enable |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_angl0_label | + | │ ├── in_angl0_en |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 in_angl0_raw | + | │ ├── in_angl0_index |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 in_angl0_scale | + | │ ├── in_angl0_type |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_angl1_label | + | │ ├── in_anglvel0_en |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_anglvel0_label | + | │ ├── in_anglvel0_index |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 in_anglvel0_raw | + | │ ├── in_anglvel0_type |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 in_anglvel0_scale | + | │ ├── in_timestamp_en |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 in_phase0_label | + | │ ├── in_timestamp_index |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 name | + | │ ├── in_timestamp_type |
- | lrwxrwxrwx 1 root root 0 Dec 5 16:05 of_node -> ../ | + | │ ├── length |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 out_altvoltage0_frequency | + | │ └── watermark |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 out_altvoltage0_frequency_available | + | ├── |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 out_altvoltage0_label | + | ├── |
- | drwxr-xr-x 2 root root 0 Dec 5 16:05 power | + | ├── |
- | drwxr-xr-x 2 root root 0 Dec 5 16:05 scan_elements | + | │ ├── in_altvoltage0_mag_rising_label |
- | lrwxrwxrwx 1 root root 0 Dec 5 16:05 subsystem -> ../ | + | │ ├── in_altvoltage0_mag_rising_reset_max |
- | drwxr-xr-x 2 root root 0 Dec 5 17:42 trigger | + | │ ├── in_altvoltage0_mag_rising_reset_max_available |
- | -rw-r--r-- 1 root root 4096 Dec 5 16:05 uevent | + | │ ├── in_altvoltage0_mag_rising_reset_min |
- | -r--r--r-- 1 root root 4096 Dec 5 16:05 waiting_for_supplier | + | │ ├── in_altvoltage0_mag_rising_reset_min_available |
+ | │ ├── in_altvoltage0_mag_rising_value | ||
+ | │ ├── in_altvoltage0_mag_rising_value_available | ||
+ | │ ├── in_altvoltage0_thresh_falling_label | ||
+ | │ ├── in_altvoltage0_thresh_falling_value | ||
+ | │ ├── in_altvoltage0_thresh_falling_value_available | ||
+ | │ ├── in_altvoltage0_thresh_rising_label | ||
+ | │ ├── in_altvoltage0_thresh_rising_value | ||
+ | │ ├── in_altvoltage0_thresh_rising_value_available | ||
+ | │ ├── in_altvoltage1_mag_either_label | ||
+ | │ ├── in_altvoltage2_mag_either_label | ||
+ | │ ├── in_angl1_thresh_rising_hysteresis | ||
+ | │ ├── in_angl1_thresh_rising_hysteresis_available | ||
+ | │ ├── in_angl1_thresh_rising_label | ||
+ | │ ├── in_angl1_thresh_rising_value | ||
+ | │ ├── in_angl1_thresh_rising_value_available | ||
+ | │ ├── in_anglvel0_mag_rising_label | ||
+ | │ ├── in_phase0_mag_rising_label | ||
+ | │ ├── in_phase0_mag_rising_value | ||
+ | │ └── in_phase0_mag_rising_value_available | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | ├── | ||
+ | │ ├── autosuspend_delay_ms | ||
+ | │ ├── control | ||
+ | │ ├── runtime_active_time | ||
+ | │ ├── runtime_status | ||
+ | │ └── runtime_suspended_time | ||
+ | ├── | ||
+ | │ ├── in_angl0_en | ||
+ | │ ├── in_angl0_index | ||
+ | │ ├── in_angl0_type | ||
+ | │ ├── in_anglvel0_en | ||
+ | │ ├── in_anglvel0_index | ||
+ | │ ├── in_anglvel0_type | ||
+ | │ ├── in_timestamp_en | ||
+ | │ ├── in_timestamp_index | ||
+ | │ └── in_timestamp_type | ||
+ | ├── | ||
+ | ├── | ||
+ | │ └── current_trigger | ||
+ | ├── | ||
+ | └── | ||
analog@setup-2-zed:/ | analog@setup-2-zed:/ | ||
Line 174: | Line 229: | ||
analog@setup-2-zed:/ | analog@setup-2-zed:/ | ||
34115 | 34115 | ||
+ | </ | ||
+ | |||
+ | Hysteresis can be enabled or disabled this way. To do so, first check the output of in_angl0_hysteresis_available: | ||
+ | |||
+ | <WRAP box bggreen>< | ||
+ | < | ||
+ | root@setup-2-zed:/ | ||
+ | 0 1 | ||
+ | </ | ||
+ | |||
+ | To turn hysteresis off, write the first value from the output to in_angl0_hysteresis: | ||
+ | |||
+ | <WRAP box bggreen>< | ||
+ | < | ||
+ | root@setup-2-zed:/ | ||
+ | </ | ||
+ | |||
+ | To turn it on, write the second value (which is dependent on the assigned bits for resolution and may not always be 1): | ||
+ | |||
+ | <WRAP box bggreen>< | ||
+ | < | ||
+ | root@setup-2-zed:/ | ||
</ | </ | ||
===== Triggered buffer ===== | ===== Triggered buffer ===== | ||
- | To generate samples using the triggered buffer, you will need a trigger. You can create an hrtimer trigger like this: | + | To generate samples using the triggered buffer, you will need a trigger. You can create an hrtimer trigger |
- | '' | + | |
- | You can grab some samples like this to connect | + | <WRAP box bggreen>< |
- | '' | + | < |
+ | root@setup-2-zed:~# mkdir / | ||
+ | root@setup-2-zed: | ||
+ | WARNING: High-speed mode not enabled | ||
+ | 00000000 | ||
+ | 00000010 | ||
+ | 00000020 | ||
+ | 00000030 | ||
+ | 00000040 | ||
+ | 00000050 | ||
+ | 00000060 | ||
+ | 00000070 | ||
+ | 00000080 | ||
+ | 00000090 | ||
+ | 000000a0 | ||
+ | 000000b0 | ||
+ | 000000c0 | ||
+ | 000000d0 | ||
+ | 000000e0 | ||
+ | 000000f0 | ||
+ | ... | ||
+ | </ | ||
<note important> | <note important> | ||
For other apps, we probably want a high sample rate. You can change the rate like this: | For other apps, we probably want a high sample rate. You can change the rate like this: | ||
- | '' | + | |
+ | <WRAP box bggreen>< | ||
+ | < | ||
+ | root@setup-2-zed: | ||
+ | 10000.000000 | ||
+ | </ | ||
===== Reading IIO Events ===== | ===== Reading IIO Events ===== | ||
Line 195: | Line 297: | ||
Fault to event mapping: | Fault to event mapping: | ||
- | ^ Fault | + | ^ Fault |
- | |Sine/ | + | |Sine/ |
- | |Sine/ | + | |Sine/ |
- | |Sine/ | + | |Sine/ |
- | |Sine/ | + | |Sine/ |
- | |Tracking error exceeds LOT | D3 | angl1 | thresh | rising | | + | |Tracking error exceeds LOT | D3 | angl1 | thresh | rising |
- | |Velocity exceeds maximum tracking rate | D2 | anglvel0 | + | |Velocity exceeds maximum tracking rate | D2 | anglvel0 |
- | |Phase error exceeds phase lock range | D1 | phase0 | + | |Phase error exceeds phase lock range | D1 | phase0 |
- | |Configuration parity error | D0 | *writes to kernel log* | | + | |Configuration parity error | D0 | *writes to kernel log* | | |
- | + | ||
- | [3]: The chip does not differentiate between fault on sine vs. cosine so | + | |
- | there will also be an event on the altvoltage2 channel. | + | |
====== Usage With the EVAL-AD2S1210SDZ Evaluation Board ====== | ====== Usage With the EVAL-AD2S1210SDZ Evaluation Board ====== | ||
Line 215: | Line 313: | ||
==== Wiring ==== | ==== Wiring ==== | ||
- | ^ AD2S1210 Pin ^ Eval Board Pin ^ RPi Header Pin ^ RPi Function ^ | + | ^ AD2S1210 Pin ^ Eval Board Pin ^ RPi Header Pin ^ RPi Function |
- | | RES0 | LK6 [1] | 15 | GPIO22 | | + | | RES0 | LK6 | 15 | GPIO22 |
- | | RES1 | LK7 [1] | 16 | GPIO23 | | + | | RES1 | LK7 | 16 | GPIO23 |
| A0 | J4-12 | 18 | GPIO24 | | | A0 | J4-12 | 18 | GPIO24 | | ||
| A1 | J4-11 | 22 | GPIO25 | | | A1 | J4-11 | 22 | GPIO25 | | ||
Line 232: | Line 330: | ||
| CS | J4-2, J4-6 | DGND | | | CS | J4-2, J4-6 | DGND | | ||
- | ^ Eval Board Signal ^ Eval Board Jumper ^ Position ^ | + | ^ Eval Board Signal ^ Eval Board Jumper ^ Position |
- | | SAMPLE | LK1 | B | | + | | SAMPLE | LK1 | B | | |
- | | CS | LK2 | C | | + | | CS | LK2 | C | | |
- | | RD | LK3 | C | | + | | RD | LK3 | C | | |
- | | A0 | LK 4 | C | | + | | A0 | LK 4 | C | | |
- | | A1 | LK5 | C | | + | | A1 | LK5 | C | | |
- | | RES0 | LK6 [1] | C | | + | | RES0 | LK6 | C | There aren’t J4 pins for RES0/1 so have to use jumper pins. It is also possible to hard-wire resolution pins RES0/1, but device tree would need to be changed accordingly. |
- | | RES1 | LK7 [1] | C | | + | | RES1 | LK7 | C | There aren’t J4 pins for RES0/1 so have to use jumper pins. It is also possible to hard-wire resolution pins RES0/1, but device tree would need to be changed accordingly. |
- | | SOE | LK9 | B | | + | | SOE | LK9 | B | | |
- | | VDRIVE | LK703 | B | | + | | VDRIVE | LK703 | B | | |
- | + | ||
- | [1] There aren’t J4 pins for RES0/1 so have to use jumper pins. It is also possible to hard-wire resolution pins RES0/1, but device tree would need to be changed accordingly. | + | |
==== Device Tree ==== | ==== Device Tree ==== | ||
Line 250: | Line 346: | ||
Overlay: [[https:// | Overlay: [[https:// | ||
+ | |||
+ | ==== Sample Images ==== | ||
+ | |||
+ | Eval board connections: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | Raspberry Pi connections: | ||
+ | |||
+ | {{: | ||
===== Zedboard ===== | ===== Zedboard ===== | ||
- | See [[: | + | {{: |
+ | |||
+ | See [[: | ||
====== More Information ====== | ====== More Information ====== | ||
{{page> | {{page> |