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This version (18 Feb 2013 15:48) was approved by larsc.The Previously approved version (20 Nov 2012 10:42) is available.Diff

AD9523 Low Jitter Clock Generator Linux Driver

Supported Devices

Evaluation Boards

Datasheets

Description

This is a Linux industrial I/O (IIO) subsystem driver, targeting serial interface PLL Synthesizers. The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc). See IIO for more information.

Source Code

Status

Source Mainlined?
git Yes

Files

Example platform device initialization

For compile time configuration, it’s common Linux practice to keep board- and application-specific configuration out of the main driver file, instead putting it into the board support file.

For devices on custom boards, as typical of embedded and SoC-(system-on-chip) based hardware, Linux uses platform_data to point to board-specific structures describing devices and how they are connected to the SoC. This can include available ports, chip variants, preferred modes, default initialization, additional pin roles, and so on. This shrinks the board-support packages (BSPs) and minimizes board and application specific #ifdefs in drivers.

21 Oct 2010 16:10 · Michael Hennerich

The reference frequency and GPIO numbers may vary between boards. The platform_data for the device's “struct device” holds this information.

/**
 * struct ad9523_channel_spec - Output channel configuration
 *
 * @channel_num: Output channel number.
 * @divider_output_invert_en: Invert the polarity of the output clock.
 * @sync_ignore_en: Ignore chip-level SYNC signal.
 * @low_power_mode_en: Reduce power used in the differential output modes.
 * @use_alt_clock_src: Channel divider uses alternative clk source.
 * @output_dis: Disables, powers down the entire channel.
 * @driver_mode: Output driver mode (logic level family).
 * @divider_phase: Divider initial phase after a SYNC. Range 0..63
		   LSB = 1/2 of a period of the divider input clock.
 * @channel_divider: 10-bit channel divider.
 * @extended_name: Optional descriptive channel name.
 */
 
struct ad9523_channel_spec {
	unsigned		channel_num;
	bool			divider_output_invert_en;
	bool			sync_ignore_en;
	bool			low_power_mode_en;
				 /* CH0..CH3 VCXO, CH4..CH9 VCO2 */
	bool			use_alt_clock_src;
	bool			output_dis;
	enum outp_drv_mode	driver_mode;
	unsigned char		divider_phase;
	unsigned short		channel_divider;
	char			extended_name[16];
};
 
/**
 * struct ad9523_platform_data - platform specific information
 *
 * @vcxo_freq: External VCXO frequency in Hz
 * @refa_diff_rcv_en: REFA differential/single-ended input selection.
 * @refb_diff_rcv_en: REFB differential/single-ended input selection.
 * @zd_in_diff_en: Zero Delay differential/single-ended input selection.
 * @osc_in_diff_en: OSC differential/ single-ended input selection.
 * @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
 * @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
 * @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
 * @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
 * @refa_r_div: PLL1 10-bit REFA R divider.
 * @refb_r_div: PLL1 10-bit REFB R divider.
 * @pll1_feedback_div: PLL1 10-bit Feedback N divider.
 * @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
 * @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
 * @osc_in_feedback_en: PLL1 feedback path, local feedback from
 *			the OSC_IN receiver or zero delay mode
 * @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
 * @ref_mode: Reference selection mode.
 * @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
 * @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
 * @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
 * @pll2_freq_doubler_en: PLL2 frequency doubler enable.
 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
 * @pll2_vco_diff_m1: VCO1 divider, range 3..5.
 * @pll2_vco_diff_m2: VCO2 divider, range 3..5.
 * @rpole2: PLL2 loop filter Rpole resistor value.
 * @rzero: PLL2 loop filter Rzero resistor value.
 * @cpole1: PLL2 loop filter Cpole capacitor value.
 * @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
 * @num_channels: Array size of struct ad9523_channel_spec.
 * @channels: Pointer to channel array.
 * @name: Optional alternative iio device name.
 */
 
struct ad9523_platform_data {
	unsigned long vcxo_freq;
 
	/* Differential/ Single-Ended Input Configuration */
	bool				refa_diff_rcv_en;
	bool				refb_diff_rcv_en;
	bool				zd_in_diff_en;
	bool				osc_in_diff_en;
 
	/*
	 * Valid if differential input disabled
	 * if false defaults to pos input
	 */
	bool				refa_cmos_neg_inp_en;
	bool				refb_cmos_neg_inp_en;
	bool				zd_in_cmos_neg_inp_en;
	bool				osc_in_cmos_neg_inp_en;
 
	/* PLL1 Setting */
	unsigned short			refa_r_div;
	unsigned short			refb_r_div;
	unsigned short			pll1_feedback_div;
	unsigned short			pll1_charge_pump_current_nA;
	bool				zero_delay_mode_internal_en;
	bool				osc_in_feedback_en;
	enum pll1_rzero_resistor	pll1_loop_filter_rzero;
 
	/* Reference */
	enum ref_sel_mode		ref_mode;
 
	/* PLL2 Setting */
	unsigned int			pll2_charge_pump_current_nA;
	unsigned char			pll2_ndiv_a_cnt;
	unsigned char			pll2_ndiv_b_cnt;
	bool				pll2_freq_doubler_en;
	unsigned char			pll2_r2_div;
	unsigned char			pll2_vco_diff_m1; /* 3..5 */
	unsigned char			pll2_vco_diff_m2; /* 3..5 */
 
	/* Loop Filter PLL2 */
	enum rpole2_resistor		rpole2;
	enum rzero_resistor		rzero;
	enum cpole1_capacitor		cpole1;
	bool				rzero_bypass_en;
 
	/* Output Channel Configuration */
	int				num_channels;
	struct ad9523_channel_spec	*channels;
 
	char				name[SPI_NAME_SIZE];
};
struct ad9523_channel_spec ad9523_channels[] = {
	{	/* ZD output */
		.channel_num = 0,
		.extended_name = "ZD_OUTPUT",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = LVDS_4mA,
		.divider_phase = 0,
		.channel_divider = 8,
		.use_alt_clock_src = false,
		.output_dis = false,
	},
	{	/* DAC CLK */
		.channel_num = 1,
		.extended_name = "DAC_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = LVPECL_8mA,
		.divider_phase = 0,
		.channel_divider = 2,
	},
	{	/* ADC CLK */
		.channel_num = 2,
		.extended_name = "ADC_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = LVDS_7mA,
		.divider_phase = 0,
		.channel_divider = 4,
	},
	{	/* DAC REF CLK */
		.channel_num = 4,
		.extended_name = "DAC_REF_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = LVDS_4mA,
		.divider_phase = 0,
		.channel_divider = 16,
	},
	{	/* TX LO REF */
		.channel_num = 5,
		.extended_name = "TX_LO_REF_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = CMOS_CONF3, /* HiZ on - */
		.divider_phase = 0,
		.channel_divider = 8,
	},
	{	/* DAC DCO */
		.channel_num = 6,
		.extended_name = "DAC_DCO_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = LVDS_7mA,
		.divider_phase = 0,
		.channel_divider = 2,
	},
	{	/* ADC SYNC */
		.channel_num = 8,
		.extended_name = "ADC_SYNC_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = CMOS_CONF3, /* HiZ on - */
		.divider_phase = 1,
		.channel_divider = 32,
		.output_dis = false,
	},
	{	/* RX LO REF */
		.channel_num = 9,
		.extended_name = "RX_LO_REF_CLK",
		.divider_output_invert_en = false,
		.sync_ignore_en = false,
		.low_power_mode_en = false,
		.driver_mode = CMOS_CONF3, /* HiZ on - */
		.divider_phase = 0,
		.channel_divider = 8,
	},
};
 
struct ad9523_platform_data ad9523_pdata_lpc = {
	.vcxo_freq = 122880000,
 
	/* Single-Ended Input Configuration */
	.refa_diff_rcv_en = true,
	.refb_diff_rcv_en = false,
	.zd_in_diff_en = true,
	.osc_in_diff_en = false,
	.osc_in_cmos_neg_inp_en = true,
 
	.refa_r_div = 0,
	.refb_r_div = 0,
	.pll1_feedback_div = 4,
	.pll1_charge_pump_current_nA = 2000,
	.zero_delay_mode_internal_en = true,
	.osc_in_feedback_en = false,
	.refb_cmos_neg_inp_en = true,
	.pll1_loop_filter_rzero = 3,
 
	.ref_mode = REVERT_TO_REFA,
 
	.pll2_charge_pump_current_nA = 420000,
	.pll2_ndiv_a_cnt = 0,
	.pll2_ndiv_b_cnt = 3,
	.pll2_freq_doubler_en = true,
	.pll2_r2_div = 1,
	.pll2_vco_diff_m1 = 3,
	.pll2_vco_diff_m2 = 3,
 
	.rpole2 = 0,
	.rzero = 2,
	.cpole1 = 2,
	.rzero_bypass_en = false,
 
	/* Output Channel Configuration */
	.num_channels = ARRAY_SIZE(ad9523_channels),
	.channels = ad9523_channels,
	.name = "ad9523-lpc"
};

Declaring SPI slave devices

Unlike PCI or USB devices, SPI devices are not enumerated at the hardware level. Instead, the software must know which devices are connected on each SPI bus segment, and what slave selects these devices are using. For this reason, the kernel code must instantiate SPI devices explicitly. The most common method is to declare the SPI devices by bus number.

This method is appropriate when the SPI bus is a system bus, as in many embedded systems, wherein each SPI bus has a number which is known in advance. It is thus possible to pre-declare the SPI devices that inhabit this bus. This is done with an array of struct spi_board_info, which is registered by calling spi_register_board_info().

For more information see: Documentation/spi/spi-summary

21 Oct 2010 16:10 · Michael Hennerich

Depending on the IC used, you may need to set the modalias accordingly, matching your part name. It may also required to adjust max_speed_hz. Please consult the datasheet, for maximum spi clock supported by the device in question.

static struct spi_board_info board_spi_board_info[] __initdata = {
#if defined(CONFIG_AD9523) || defined(CONFIG_AD9523_MODULE)
	{
		.modalias = "ad9523-1",
		.max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 3,
		.platform_data = &ad9523_pdata_lpc, /* spi_driver specific config */
		.mode = SPI_MODE_0, /* optional set SPI_3WIRE */
	},
};
static int __init board_init(void)
{
	[--snip--]
 
	spi_register_board_info(board_spi_board_info, ARRAY_SIZE(board_spi_board_info));
 
	[--snip--]
 
	return 0;
}
arch_initcall(board_init);

Adding Linux driver support

Configure kernel with “make menuconfig” (alternatively use “make xconfig” or “make qconfig”)

The AD9523 Driver depends on CONFIG_SPI

Linux Kernel Configuration
	Device Drivers  --->
		<*>     Industrial I/O support --->
		    --- Industrial I/O support
				Frequency Synthesizers DDS/PLL  --->
					Clock Generator/Distribution  ---> 
		    [--snip--]
				<*> Analog Devices AD9523 Low Jitter Clock Generator 
		    [--snip--]

Hardware configuration

Driver testing

Each and every IIO device, typically a hardware chip, has a device folder under /sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under every of these directory folders reside a set of files, depending on the characteristics and features of the hardware device in question. These files are consistently generalized and documented in the IIO ABI documentation. In order to determine which IIO deviceX corresponds to which hardware device, the user can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the sequence in which the iio device drivers are loaded/registered is constant, the numbering is constant and may be known in advance.

02 Mar 2011 15:16 · Michael Hennerich

This specifies any shell prompt running on the target

root:/> cd /sys/bus/iio/devices/
root:/sys/bus/iio/devices> ls
iio:device0
root:/sys/bus/iio/devices> iio:device0

root:/> ls -l
total 0
drwxr-xr-x    2 root     root             0 Jan  1 00:00 .
drwxr-xr-x    3 root     root             0 Jan  1 00:00 ..
-r--r--r--    1 root     root          4096 Jan  1 00:00 dev
-r--r--r--    1 root     root          4096 Jan  1 00:00 name
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage0_ZD_OUTPUT_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage0_ZD_OUTPUT_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage0_ZD_OUTPUT_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage1_DAC_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage1_DAC_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage1_DAC_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage2_ADC_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage2_ADC_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage2_ADC_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage4_DAC_REF_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage4_DAC_REF_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage4_DAC_REF_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage5_TX_LO_REF_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage5_TX_LO_REF_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage5_TX_LO_REF_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage6_DAC_DCO_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage6_DAC_DCO_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage6_DAC_DCO_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage8_ADC_SYNC_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage8_ADC_SYNC_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage8_ADC_SYNC_CLK_raw
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage9_RX_LO_REF_CLK_frequency
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage9_RX_LO_REF_CLK_phase
-rw-r--r--    1 root     root          4096 Jan  1 00:00 out_altvoltage9_RX_LO_REF_CLK_raw
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll1_locked
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll1_reference_clk_a_present
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll1_reference_clk_b_present
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll1_reference_clk_test_present
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll2_feedback_clk_present
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll2_locked
-r--r--r--    1 root     root          4096 Jan  1 00:00 pll2_reference_clk_present
--w-------    1 root     root          4096 Jan  1 00:00 store_eeprom
lrwxrwxrwx    1 root     root             0 Jan  1 00:00 subsystem -> ../../../../../../../../../bus/iio
--w-------    1 root     root          4096 Jan  1 00:00 sync_dividers
-rw-r--r--    1 root     root          4096 Jan  1 00:00 uevent
-r--r--r--    1 root     root          4096 Jan  1 00:00 vcxo_clk_present

Show device name

This specifies any shell prompt running on the target

root:/> cd /sys/bus/iio/devices/iio\:device0/
root:/> cat name
ad9523-lpc

Set ChannelY Output Frequency

/sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency

Output frequency for channel Y in Hz. The number must always be specified and unique if the output corresponds to a single channel.

This specifies any shell prompt running on the target

root:/> cat out_altvoltage1_DAC_CLK_frequency
491520000
root:/> echo 245760000 > out_altvoltage1_DAC_CLK_frequency
root:/> cat out_altvoltage1_DAC_CLK_frequency
245760000

Set ChannelY Output Divider Phase

/sys/bus/iio/devices/iio:deviceX/out_altvoltageY_phase

Phase in radians of one frequency/clock output Y (out_altvoltageY) relative to another frequency/clock output (out_altvoltageZ) of the device X. The number must always be specified and unique if the output corresponds to a single channel.

This specifies any shell prompt running on the target

root:/> cat out_altvoltage1_DAC_CLK_phase
0.000000
root:/> echo 3.142 >  out_altvoltage1_DAC_CLK_phase
root:/> cat out_altvoltage1_DAC_CLK_phase
3.1415920

Disable / Power Down ChannelY

/sys/bus/iio/devices/iio:deviceX/out_altvoltageY_phase

Writing '0' powers down channelY, while writing any any value > 0 enables the channel.

This specifies any shell prompt running on the target

root:/> cat out_altvoltage1_DAC_CLK_raw
1
root:/> echo 0 >  out_altvoltage1_DAC_CLK_raw
root:/> cat out_altvoltage1_DAC_CLK_raw
0

Query Device Status

/sys/bus/iio/devices/iio:deviceX/pll1_locked
/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present
/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present
/sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present
/sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present
/sys/bus/iio/devices/iio:deviceX/pll2_locked
/sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present
/sys/bus/iio/devices/iio:deviceX/vcxo_clk_present

Reading returns either '1' or '0'. '1' means that the clock in question is present or the pllY is locked. '0' means that the clock is missing or the pllY is unlocked.

This specifies any shell prompt running on the target

root:/> cat pll1_locked
1

root:/> grep ”” pll* vcxo*
pll1_locked:1
pll1_reference_clk_a_present:1
pll1_reference_clk_b_present:0
pll1_reference_clk_test_present:0
pll2_feedback_clk_present:1
pll2_locked:1
pll2_reference_clk_present:1
vcxo_clk_present:1

Save Current Device Config to EEPROM

/sys/bus/iio/devices/iio:deviceX/store_eeprom

Writing '1' stores the current device configuration into on-chip EEPROM. After power-up or chip reset the device will automatically load the saved configuration.

This specifies any shell prompt running on the target

root:/> echo 1 > store_eeprom

SYNC Device

/sys/bus/iio/devices/iio:deviceX/sync_dividers

Writing '1' triggers the clock distribution synchronization functionality. All dividers are reset and the channels start with their predefined phase offsets (out_altvoltageY_phase). Writing this file has the effect as driving the external /SYNC pin low.

This specifies any shell prompt running on the target

root:/> echo 1 > sync_dividers

More Information