ADXL345 Xilinx Pmod FPGA Reference Design

Introduction

The ADXL345 is a high resolution (13-bits)3-axis accelerometer for measurements at and up to +16g. This reference design allows full programming of the device and reports the measurements along the 3 axes as well as single tap, double tap and free fall.

HW Platform(s): Spartan-6 LX9 Microboard (Avnet), PMOD-ACL ADXL345 (Digilent)
System: Microblaze, AXI, UART

Quick Start Guide

The bit file provided in the project *.tar.gz file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

Required Hardware

LX9 microboard
PMOD-ACL ADXL345 card

Required Software

Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
A UART terminal (Tera Term/Hyperterminal), Baud rate 115200.

Running Demo (SDK) Program

If you are not familiar with LX9 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm for details.

Extract the project from the archive file (cf_adxl345.tar.gz) to the location you desire.

To begin, connect the PMOD-ACL board to J4 connector of LX9 board (see image below). You may use a extension cable so that you could move the ADXL345 around/along various axes. Also both 12 pin and 6 pin connections are supported. Only the interrupt driven mode requires the 12 pin connection. Connect the USB cables from the PC to the board.

Start IMPACT, and initialze the JTAG chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to 115200 baud rate) and then program the device using the bit file provided in the project *.tar.gz archive, located in the “sw” folder (../cf_adxl345/sw/cf_adxl345.bit).

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the ADXL345 device, the program continously monitors the X, Y and Z axes values as well as single tap, double tap and free fall detection. You may quit the program any time by pressing 'q' and then the 'Enter' key.

Using the reference design

Functional Description

The reference design is a simple SPI interface for the ADXL345. The software programs the device, monitors and reports the axes, single tap, double tap and free fall. The information is displayed on UART.

The hardware supports both 12 pin and 6 pin connections.

The hardware SPI access allows read or write of any ADXL345 registers via the address, write and read data registers. A status output is connected to the 4 LED(s) on board as follows :-

STATUS_FF_ST: Free fall/single tap
STATUS_FF_DT: Free fall/double tap
STATUS_XY: X/Y axis change
STATUS_Z: Z axis change

In most cases, a simple SPI access is all the software need. However, in order to reduce the overhead on software running on Microblaze SDK (to keep I/D BRAM small), a hardware assisted mode is provided. In this mode, hardware mirrors a few key registers of ADXL345 in it's own address space.

The hardware supports three modes of operation:

Software triggered: In this mode, software must initiate the read to update the mirrored registers.
Interrupt triggered: In this mode, ADXL345's INT1, INT2 pins trigger update of the mirrored registers.
Free run: In this mode, hardware free runs and continously updates the mirrored registers.

Registers

QW Address¹	Bits	Default	Name	Description
0x00	7	0	mode	Free run (0x1) or sw/hw controlled (0x0).
	6	0	int_inv	Invert (0x1) interrupt pins.
	5	0	access	SPI access sw (0x1) or hw (0x0).
	4	0	trigger	Software trigger, requires a 0x0 to 0x1 transition.
	3:0	0	status	Software status, ignored if hardware is active.
0x01	31	0	rwn	SPI access, read (0x1) or write (0x0).
	29:24	0	addr	SPI access, address.
	23:16	0	wdata	SPI access, write data.
	15	0	done	SPI access, complete (0x1) or busy (0x0).
	7:0	0	rdata	SPI access, read data.
The following registers are provided for simultaneous access in free run and interrupt triggered modes
0x03	15:0	0	x_axis	X Axis data.
0x04	15:0	0	y_axis	Y Axis data.
0x05	15:0	0	z_axis	Z Axis data.
0x06	15:0	0	x_axis	ACT/TAP data.
0x07	15:0	0	x_axis	INT source data.
0x08	15:0	0	x_axis	FIFO status data.
0x09	3:0	0	state	Hw state (for debug purposes only).
1. For AXI-Lite byte addresses, multiply by 4.

Notes

PMOD-ACL must be connected to J4, with pin 1 matching up on both the connectors.
UART must be set to 115200 baudrate.

A debug data and trigger port is provided for internal monitoring of all the signals in the design.

Downloads

Reference design source code

More information

ask questions about the FPGA reference design

Wiki

Analog Devices Wiki

Table of Contents

ADXL345 Xilinx Pmod FPGA Reference Design

Introduction