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resources:fpga:xilinx:pmod:adxl345 [31 Jan 2013 08:57] – old revision restored Alexandru.Tofanresources:fpga:xilinx:pmod:adxl345 [09 Jan 2021 00:57] (current) – user interwiki links Robin Getz
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 **HW Platform(s):**  **HW Platform(s):** 
-   * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]  +   * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]  
-   * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]  +   * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]] 
-   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL|PmodACL (Digilent)]] \\+   * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] \\
  
-**System:** Microblaze, AXI, UART \\ 
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
  
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 ==== Required Hardware ==== ==== Required Hardware ====
-  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]+  * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]
   * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]     * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]  
 +  * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] 
   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL|PmodACL (Digilent)]]   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-ACL|PmodACL (Digilent)]]
  
 ==== Required Software ==== ==== Required Software ====
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard or 9600 for the Digilent Nexys™3 Board.+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
  
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ +<WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ 
-If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. +If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.\\ 
-</note> +If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx]] for details.</WRAP>
- +
-Extract the project from the archive file (ADXL345_<board_name>.zip) to the location you desire. +
  
 ==== Avnet LX9 MicroBoard Setup ==== ==== Avnet LX9 MicroBoard Setup ====
 +
 +Extract the project from the archive file (ADXL345_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodACL to J5 connector of LX9 board (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector. To begin, connect the PmodACL to J5 connector of LX9 board (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
 +
 +Extract the project from the archive file (ADXL345_<board_name>.zip) to the location you desire. 
  
 To begin, connect the PmodACL to JA connector of NEXYS3 board (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). To begin, connect the PmodACL to JA connector of NEXYS3 board (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
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 {{:resources:fpga:xilinx:pmod:pmodacl_nexys3.jpg?200|PmodACL and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodacl_nexys3.jpg?200|PmodACL and Nexys™3}}
  
-==== FPGA Configuration ====+==== Avnet ZedBoard ==== 
 + 
 +To begin, connect the PmodACL to JA1 connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodacl_zed.jpg?200|PmodACL and ZedBoard}} 
 + 
 +==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ====
  
 Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../adxl345/sw/ADXL345.bit). Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to appropiate baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../adxl345/sw/ADXL345.bit).
  
 {{:resources:fpga:xilinx:pmod:PmodACLImpact.jpg?200|Programming FPGA in IMPACT}} {{:resources:fpga:xilinx:pmod:PmodACLImpact.jpg?200|Programming FPGA in IMPACT}}
 +
 +==== FPGA Configuration for ZedBoard ====
 +
 +Run the **download.bat** script from the "../bin" folder downloaded from the github (see the links in the download section of the wiki page). 
 +The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards.
 +
 +<WRAP center round tip 80%>
 +If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path.
 +</WRAP>
  
 If programming was successful, the **Main Menu** will apear in your UART terminal, as seen in the picture below. There are 7 options. Pressing [e], [d], [a], [s], [r], [t] or [q] key will allow you to select the desired option. If programming was successful, the **Main Menu** will apear in your UART terminal, as seen in the picture below. There are 7 options. Pressing [e], [d], [a], [s], [r], [t] or [q] key will allow you to select the desired option.
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 {{:resources:fpga:xilinx:pmod:pmodacl_menu6.jpg?600|Acquisition Rate}}\\ {{:resources:fpga:xilinx:pmod:pmodacl_menu6.jpg?600|Acquisition Rate}}\\
  
-**Select Tap Interrupts** allows enabling or disabling tap interrupts. Desired option is selected by pressing [1] to [4]. If the tap option selected is [1] or [3], after a single tap, D2 (LX9) / LD0 (Nexys3) will be ON. If the tap option selected is [2] or [3], after two consecutive taps, D3 and D2 (LX9) / LD1 and LD0 (Nexys3) will both be on at the same time. If the tap option selected is [4], no LEDs will be ON after a single or double tap.+**Select Tap Interrupts** allows enabling or disabling tap interrupts. Desired option is selected by pressing [1] to [4]. If the tap option selected is [1] or [3], after a single tap, D2 (LX9) / LD0 (Nexys3 and ZedBoard) will be ON. If the tap option selected is [2] or [3], after two consecutive taps, D3 and D2 (LX9) / LD1 and LD0 (Nexys3 and ZedBoard) will both be on at the same time. If the tap option selected is [4], no LEDs will be ON after a single or double tap.
  
 {{:resources:fpga:xilinx:pmod:pmodacl_menu7.jpg?600|Select Tap Interrupts}}\\ {{:resources:fpga:xilinx:pmod:pmodacl_menu7.jpg?600|Select Tap Interrupts}}\\
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 ==== Functional Description ==== ==== Functional Description ====
  
-The reference design is a SPI interface used to communicate with the device. The software programs the ADXL345s internal registers, and afterwards reads desired data from the device and prints it via UART. Three Interrupt signals are used in the design: one coming from the ADXL345, one from the UART and a timer interrupt (used for single and double tap LED signaling).+The reference design is a SPI interface used to communicate with the device. The software programs the ADXL345 internal registers, and afterwards reads desired data from the device and prints it via UART. Three Interrupt signals are used in the design: one coming from the ADXL345, one from the UART and a timer interrupt (used for single and double tap LED signaling).
  
-<note important>+ 
 + 
 +<WRAP round important 80%> 
 +\\
   * Connecting the PmodACL to the boards using an extension cable provides ease of use.   * Connecting the PmodACL to the boards using an extension cable provides ease of use.
-  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board. +  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. 
-</note>+\\ 
 +</WRAP>
  
 +<WRAP round important 80%>
 +When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in "system_config.h":
  
 +<code c>
 +// Select between PS7 or AXI Interface
 +#define USE_PS7 1
 +// SPI used in the design
 +#define USE_SPI 1
 +// I2C used in the design
 +#define USE_I2C 0
 +// Timer (+interrupts) used in the design
 +#define USE_TIMER 1
 +// External interrupts used in the design
 +#define USE_EXTERNAL     1
 +// GPIO used in the design
 +#define USE_GPIO         1
 +</code>
 +
 +</WRAP>
 ===== Downloads ===== ===== Downloads =====
-<WRAP round download 50%> +<WRAP round download 80%> 
-{{:resources:fpga:xilinx:pmod:adxl345_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\ +\\ 
-{{:resources:fpga:xilinx:pmod:adxl345_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}+**Avnet LX-9 MicroBoard: **\\ 
 +    * {{:resources:fpga:xilinx:pmod:adxl345_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\ 
 + 
 +**Digilent Nexys™3:**\\ 
 +    * {{:resources:fpga:xilinx:pmod:adxl345_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}\\ 
 + 
 +**Avnet ZedBoard:**\\ 
 +    * [[https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_adv7511_zed|XPS Project]]\\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodACL|PmodACL Driver Files]]\\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/Common/sw|ZYNQ SoC Peripherals Driver Files]] \\ 
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodACL/bin|Programming Script]]\\ 
 +    
 </WRAP> </WRAP>
 +<wrap hide>
 +====== Linux Device Driver ======
 +
 +Connect PmodACL to the JA1 connector of the ZedBoard (upper row of pins).
 +
 +===== Preparing the SD Card =====
 +
 +In order to prepare the SD Card for booting Linux on the ZedBoard:
 +    * Download the device tree: [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodACL/dts|PmodACL Linux devicetree]]
 +    * Configure the kernel to include the driver for the ADXL345: [[/resources/tools-software/linux-drivers/input-misc/adxl345|Compiling the ADXL345 driver into the kernel]]
 +    * Follow the instructions on the following wiki page, but use the device tree downloaded on the previous step and the kernel configuration above
 +        * [[/resources/tools-software/linux-drivers/platforms/zynq|Linux with HDMI video output on the ZED and ZC702]]. When following those instructions make sure to copy the devicetree file that was downloaded in step 1) to arch/arm/boot/dts/zynq-zed-adv7511-pmod-acl.dts before trying to build the zynq-zed-adv7511-pmod-acl.dtb file.
 +
 +Make sure you have an HDMI monitor connected to the ZedBoard, plug in the SD Card and power on the board.
 +If everything is correct, the system should boot up. If you don't have an HDMI monitor, connect to the board via UART, Baud Rate 115200.
 +
 +There are 2 ways to test the driver.
 +    * Using the terminal window
 +    * Using a serial terminal
 +
 +===== Using the terminal window =====
 +
 +Open a new terminal window by pressing **Ctrl+Alt+T**.
 +
 +Navigate to the location of the device and identify it using the following commands:
 +<code>
 +cd /sys/bus/spi/devices/
 +ls
 +spi32765.0  spi32766.0
 +cd spi32766.0
 +cat modalias
 +spi:adxl34x
 +</code>
 +
 +If the **cat name** command doesn't return **spi:adxl34x**, then change the spi:device, and check again.
 +<code>
 +cd ..
 +cd spi32765.0
 +cat modalias
 +</code>
 +
 +To see the list of options that the ADXL345 driver provides, type:
 +<code>
 +ls
 +autosleep  disable  input     position  rate       uevent
 +calibrate  driver   modalias  power     subsystem
 +</code>
 +
 +To calibrate the device, type:
 +<code>
 +echo 1 > calibrate
 +cat calibrate
 +4,3,-218
 +</code>
 +
 +To read the position, type:
 +<code>
 +cat position
 +(1, 0, 1)
 +</code>
 +
 +{{:resources:fpga:xilinx:pmod:adxl345_linaro_terminal.jpg?600|ADXL345 Set Voltage from Terminal}}
  
 +The commands written above can also be used if not using an HDMI monitor and a wireless keyboard, by using a serial terminal, and typing the commands after the system boot-up is complete.
  
 +{{:resources:fpga:xilinx:pmod:adxl345_linux_serial.jpg?600|ADXL345 Read Voltage from Serial Terminal}}
 +</wrap>
 ===== More information ===== ===== More information =====
   * [[ez>community/fpga|ask questions about the FPGA reference design]]   * [[ez>community/fpga|ask questions about the FPGA reference design]]
   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/xilinx/pmod/adxl345.1359619054.txt.gz · Last modified: 31 Jan 2013 08:57 by Alexandru.Tofan

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