This version is outdated by a newer approved version.

This version (26 Nov 2012 11:14) was approved by Alexandru.Tofan.The Previously approved version (06 Aug 2012 12:41) is available.

This is an old revision of the document!

AD5628 Pmod Xilinx FPGA Reference Design

Introduction

The AD5628 The AD5628 is a low power, octal, 12 bit, buffered voltage-output DAC. The device operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5628 is available in both a 4 mm × 4 mm LFCSP and a 16-lead TSSOP. The AD5628 has an on-chip reference with an internal gain of 2. The AD5628 has a 1.25 V 5 ppm/°C reference, giving a full-scale output range of 2.5 V; the AD5628-2 has a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write.

HW Platform(s):

System: Microblaze, AXI, UART

Quick Start Guide

The bit file provided in the project *.zip file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

Required Hardware

Required Software

Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard or 9600 for the Digilent Nexys™3 Board.

Running Demo (SDK) Program

If you are not familiar with LX9 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm for details.
If you are not familiar with Nexys™3 and/or Xilix tools, please visit
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3 for details.

Extract the project from the archive file (AD5628_<board_name>.zip) to the location you desire.

Avnet LX9 MicroBoard Setup

To begin, connect the PmodDA4 to J4 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.

Digilent Nexys™3 Spartan-6 FPGA Board

To begin, connect the PmodDA4 to JB connector of Nexys™3 board, pins JB1 to JB6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.

FPGA Configuration

Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Connect an oscilloscope to the following outputs of PmodDA4: A,C,E,G. Program the device using the bit file provided in the project *.zip archive, located in the “sw” folder (../ad5628/sw/AD5628.bit).

If programming was successful, the Main Menu will apear in your UART terminal, as seen in the picture below. There are 3 options:

Press [1] to select Fixed Value Mode.
Press [2] to select Waveform Generation Mode.
Press [3] to select Programmable Ramp Signal Generator.

When entering Fixed Value Mode, DAC selection is automatically activated. Selecting the DAC is done by pressing [1] to [9].

Fixed Value Mode allows entering a value between 0x000 and 0xFFF, value that will be programmed in the DAC. If the number of input characters is less than 3 (e.g. ff or 76), the [Enter] key must be pressed in order to validate the input. If 3 characters are input, the value is automatically validated (in order to prevent entering more than 3 characters). Pressing the [s] key at any time will enter DAC Selection Mode.

Pressing the [q] key at any time exits the Fixed Value (or Waveform Generation) Mode and displays the Main Menu again.

When entering Waveform Generation Mode, DAC selection is automatically activated. Selecting the DAC is done by pressing [1] to [9].

Waveform Generation Mode allows selecting between 4 types of waveforms: Square, Triangle, Sawtooth and Sine waveforms. Changing between the 4 is done by pressing [1] to [4] on the keyboard. Pressing [s] at any time will enter DAC Selection Mode. Pressing [q] at any time will return to the Main Menu.

Programmable Ramp Signal Generator allows generating a programmable ramp signal. This mode can be used to test the PmodDA4 using a Digital Multimeter.

Enter time step allows setting a time step between 100 and 5000 ms.

Enter increment size allows selecting an increment size that suits your design. Values can vary from 0x000 to 0xFFF.

Select DAC allows selecting which DAC Output will be used for the Ramp Signal Generation.

Run Ramp Signal Generator will start generating the desired output.

Using the reference design

Functional Description

The reference design is a simple SPI interface used to communicate with the PmodDA4. The software programs the device sending 12-bit data values read from the keyboard input or from predefined look up tables. The user has the ability to select between two modes: a Fixed Value Mode or a Waveform Generation Mode. Communication between the user and the board is done via UART.

Connecting the PmodDA4 to the boards using an extension cable provides ease of use.
UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.

Downloads

Reference design source code for Avnet LX9 MicroBoard.
Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.

More information

ask questions about the FPGA reference design
Example questions:
- An error occurred while fetching this feed: http://ez.analog.com/community/feeds/allcontent/atom?community=2061

Wiki

Analog Devices Wiki

Table of Contents

AD5628 Pmod Xilinx FPGA Reference Design

Introduction