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resources:fpga:xilinx:pmod:ad5628 [08 Jun 2012 15:16] – Added Nexys3 and project archives Alexandru.Tofanresources:fpga:xilinx:pmod:ad5628 [09 Jan 2021 00:49] (current) – user interwiki links Robin Getz
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 **HW Platform(s):**  **HW Platform(s):** 
-   * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] +   * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]] 
    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]     * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]] 
-   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-DA4|PmodDA4 (Digilent)]] \\ +   * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] \\ 
-**System:** Microblaze, AXI, UART \\+
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
  
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 ==== Required Hardware ==== ==== Required Hardware ====
-  * [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]+  * [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm|Spartan-6 LX9 Microboard (Avnet)]]
   * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]]    * [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3|Nexys™3 Spartan-6 FPGA Board (Digilent)]] 
 +  * [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx|Avnet ZedBoard]] 
   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-DA4|PmodDA4 (Digilent)]]   * [[http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-DA4|PmodDA4 (Digilent)]]
  
  
 ==== Required Software ==== ==== Required Software ====
-  * Xilinx ISE 13.(Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.(Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.+  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200 for the Avnet LX-9 Microboard and ZedBoard or 9600 for the Digilent Nexys™3 Board.
  
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ +<WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[xilinx>products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\ 
-If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. +If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.\\ 
-</note> +If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http://www.em.avnet.com/en-us/design/drc/Pages/Zedboard.aspx]] for details.</WRAP>
- +
-Extract the project from the archive file (AD5628_<board_name>.zip) to the location you desire+
  
 ==== Avnet LX9 MicroBoard Setup ==== ==== Avnet LX9 MicroBoard Setup ====
  
-To begin, connect the PmodDA4 to J4 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+Extract the project from the archive file (AD5628_<board_name>.zip) to the location you desire.  
 + 
 +To begin, connect the PmodDA4 to J4 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
  
 {{:resources:fpga:xilinx:pmod:pmodda4.jpg?200|PmodDA4 and LX-9}} {{:resources:fpga:xilinx:pmod:pmodda4.jpg?200|PmodDA4 and LX-9}}
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
  
-To begin, connect the PmodDA4 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+Extract the project from the archive file (AD5628_<board_name>.zip) to the location you desire.  
 + 
 +To begin, connect the PmodDA4 to JB connector of Nexys™3 board, pins JB1 to JB6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
  
 {{:resources:fpga:xilinx:pmod:pmodda4_nexys3.jpg?200|PmodDA4 and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodda4_nexys3.jpg?200|PmodDA4 and Nexys™3}}
 +
 +==== Avnet ZedBoard ====
 +
 +To begin, connect the PmodDA4 to JA1 connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
 +
 +{{:resources:fpga:xilinx:pmod:pmodda4_zed.jpg?200|PmodDA4 and ZedBoard}}
 +
 +==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ====
  
 Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Connect an oscilloscope to the following outputs of PmodDA4: A,C,E,G. Program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad5628/sw/AD5628.bit). Start IMPACT, and double click "Boundary Scan". Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Connect an oscilloscope to the following outputs of PmodDA4: A,C,E,G. Program the device using the bit file provided in the project *.zip archive, located in the "sw" folder (../ad5628/sw/AD5628.bit).
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 {{:resources:fpga:xilinx:pmod:PmodDA4Impact.jpg?200|Programming FPGA in IMPACT}} {{:resources:fpga:xilinx:pmod:PmodDA4Impact.jpg?200|Programming FPGA in IMPACT}}
  
-If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD5628 device, the program will prompt you to select a waveform type from 4 available waveforms: Square, Triangle, Sawtooth or Sine waveform. Pressing a number between 1 and 4 will select a certain waveform. If you press another key again, the waveform will change to the selected one for each of the 4 channels (A, C, E and G).+==== FPGA Configuration for ZedBoard ====
  
-{{:resources:fpga:xilinx:pmod:pmodda4hyper.jpg?200|UART messeges}}+Run the **download.bat** script from the "../bin" folder downloaded from the github (see the links in the download section of the wiki page).  
 +The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards. 
 + 
 +<WRAP center round tip 80%> 
 +If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path. 
 +</WRAP> 
 + 
 +If programming was successful, the **Main Menu** will apear in your UART terminal, as seen in the picture below. 
 +There are 3 options: 
 +  * Press **[f]** to select **Fixed Value Mode**. 
 +  * Press **[w]** to select **Waveform Generation Mode**. 
 +  * Press **[p]** to select **Programmable Ramp Signal Generator**. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu1.jpg?600|Main Menu}} 
 + 
 +When entering **Fixed Value Mode**, DAC selection is automatically activated. Selecting the DAC is done by pressing **[1]** to **[9]**. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu2.jpg?600|Fixed Value Mode}} 
 + 
 +**Fixed Value Mode** allows entering a value between **0x000** and **0xFFF**, value that will be programmed in the DAC. If the number of input characters is less than 3 (e.g. ff or 76), the **[Enter]** key must be pressed in order to validate the input. If 3 characters are input, the value is automatically validated (in order to prevent entering more than 3 characters). Pressing the **[s]** key at any time will enter DAC Selection Mode. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu3.jpg?600|UART messeges}} 
 + 
 +Pressing the **[q]** key at any time exits the Fixed Value (or Waveform Generation) Mode and displays the **Main Menu** again. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu4.jpg?600|Returning to Menu}} 
 + 
 +When entering **Waveform Generation Mode**, DAC selection is automatically activated. Selecting the DAC is done by pressing **[1]** to **[9]**. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu5.jpg?600|Waveform Generation Mode}} 
 + 
 +**Waveform Generation Mode** allows selecting between 4 types of waveforms: **Square**, **Triangle**, **Sawtooth** and **Sine** waveforms. Changing between the 4 is done by pressing **[1]** to **[4]** on the keyboard. Pressing **[s]** at any time will enter DAC Selection Mode. Pressing **[q]** at any time will return to the **Main Menu**. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu6.jpg?600|Selecting Waveform type}} 
 + 
 +**Programmable Ramp Signal Generator** allows generating a programmable ramp signal. This mode can be used to test the PmodDA4 using a Digital Multimeter. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu7.jpg?600|Ramp Signal Generator Menu}} 
 + 
 +**Enter time step** allows setting a time step between **100** and **5000** ms. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu8.jpg?600|Setting time step}} 
 + 
 +**Enter increment size** allows selecting an increment size that suits your design. Values can vary from **0x000** to **0xFFF**. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu9.jpg?600|Setting step size}} 
 + 
 +**Select DAC** allows selecting which DAC Output will be used for the Ramp Signal Generation. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu10.jpg?600|Selecting DAC}} 
 + 
 +**Run Ramp Signal Generator** will start generating the desired output. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodda4_menu11.jpg?600|Running the Ramp Signal Generator}}
  
  
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 ==== Functional Description ==== ==== Functional Description ====
  
-The reference design is a simple SPI interface used to communicate with the PmodDA4. The software enables the internal voltage reference, programs the device sending 12-bit data values read from predefined look up tables. The user has the ability to change between 4 different look up tables, each one representing different waveform. Communication between the user and the board is done via UART.+The reference design is a simple SPI interface used to communicate with the PmodDA4. The software programs the device sending 12-bit data values read from the keyboard input or from predefined look up tables. The user has the ability to select between two modes: a Fixed Value Mode or Waveform Generation Mode. Communication between the user and the board is done via UART.
  
-<note important>+<WRAP round important 80%> 
 +\\
   * Connecting the PmodDA4 to the boards using an extension cable provides ease of use.   * Connecting the PmodDA4 to the boards using an extension cable provides ease of use.
-  * UART must be set to 57600 baudrate+  * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. 
-</note>+\\ 
 +</WRAP>
  
 +<WRAP round important 80%>
 +When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in "system_config.h":
 +
 +<code c>
 +// Select between PS7 or AXI Interface
 +#define USE_PS7 1
 +// SPI used in the design
 +#define USE_SPI 1
 +// I2C used in the design
 +#define USE_I2C 0
 +// Timer (+interrupts) used in the design
 +#define USE_TIMER 1
 +// External interrupts used in the design
 +#define USE_EXTERNAL     0
 +// GPIO used in the design
 +#define USE_GPIO         0
 +</code>
 +
 +</WRAP>
  
 ===== Downloads ===== ===== Downloads =====
-{{:resources:fpga:xilinx:pmod:AD5628_LX9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\ 
-{{:resources:fpga:xilinx:pmod:AD5628_NEXYS3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} 
  
 +<WRAP round download 80%>
 +\\
 +**Avnet LX-9 MicroBoard: **\\
 +    * {{:resources:fpga:xilinx:pmod:AD5628_LX9.zip|Reference design source code for Avnet LX9 MicroBoard.}}\\
 +
 +**Digilent Nexys™3:**\\
 +    * {{:resources:fpga:xilinx:pmod:AD5628_NEXYS3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}}\\
 +
 +**Avnet ZedBoard:**\\
 +    * [[https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_adv7511_zed|XPS Project]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodDA4|PmodDA4 Driver Files]]\\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/Common/sw|ZYNQ SoC Peripherals Driver Files]] \\
 +    * [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodDA4/bin|Programming Script]]\\
 +    
 +</WRAP>
 +
 +<wrap hide>
 +====== Linux Device Driver ======
 +
 +Connect PmodDA4 to the JB1 connector of the ZedBoard (upper row of pins).
 +
 +===== Preparing the SD Card =====
 +
 +In order to prepare the SD Card for booting Linux on the ZedBoard:
 +    * Download the device tree: [[https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodDA4/dts|PmodDA4 Linux devicetree]]
 +    * Follow the instructions on the following wiki page, but use the device tree downloaded on the previous step
 +        * [[/resources/tools-software/linux-drivers/platforms/zynq?s=adv7511&s=linux|Linux with HDMI video output on the ZED and ZC702]].
 +
 +Make sure you have an HDMI monitor connected to the ZedBoard, plug in the SD Card and power on the board.
 +If everything is correct, the system should boot up. If you don't have an HDMI monitor, connect to the board via UART, Baud Rate 115200.
 +
 +There are 2 ways to test the driver.
 +    * Using the terminal window
 +    * Using a serial terminal
 +
 +===== Using the terminal window =====
 +
 +Open a new terminal window by pressing **Ctrl+Alt+T**.
 +
 +Navigate to the location of the device and identify it using the following commands:
 +<code>
 +cd /sys/bus/iio/devices/
 +ls
 +iio:device0 iio:device1 trigger0
 +cd iio\:device0
 +cat name
 +ad5628-1
 +</code>
 +
 +If the **cat name** command doesn't return **ad5628-1**, then change the number of the iio:device, and check again.
 +<code>
 +cd ..
 +cd iio\:device1
 +cat name
 +</code>
 +
 +To see the list of options that the AD5628 driver provides, type:
 +<code>
 +ls
 +dev                          out_voltage4_powerdown_mode
 +name                         out_voltage4_raw
 +out_voltage0_powerdown       out_voltage4_scale
 +out_voltage0_powerdown_mode  out_voltage5_powerdown
 +out_voltage0_raw             out_voltage5_powerdown_mode
 +out_voltage0_scale           out_voltage5_raw
 +out_voltage1_powerdown       out_voltage5_scale
 +out_voltage1_powerdown_mode  out_voltage6_powerdown
 +out_voltage1_raw             out_voltage6_powerdown_mode
 +out_voltage1_scale           out_voltage6_raw
 +out_voltage2_powerdown       out_voltage6_scale
 +out_voltage2_powerdown_mode  out_voltage7_powerdown
 +out_voltage2_raw             out_voltage7_powerdown_mode
 +out_voltage2_scale           out_voltage7_raw
 +out_voltage3_powerdown       out_voltage7_scale
 +out_voltage3_powerdown_mode  out_voltage_powerdown_mode_available
 +out_voltage3_raw             power
 +out_voltage3_scale           subsystem
 +out_voltage4_powerdown       uevent
 +</code>
 +
 +To set the raw output voltage for channel A, type:
 +<code>
 +echo 1200 > out_voltage0_raw
 +</code>
 +
 +To check that the raw output voltage has been set, you can type:
 +<code>
 +cat out_voltage0_raw
 +1200
 +</code>
 +
 +If you want to set the voltage for another channel, replace **out_voltage0_raw** with, for example, **out_voltage1_raw**.
 +
 +{{:resources:fpga:xilinx:pmod:ad5628_linaro_terminal.jpg?600|AD5628 Set Voltage from Terminal}}
 +
 +The commands written above can also be used if not using an HDMI monitor and a wireless keyboard, by using a serial terminal, and typing the commands after the system boot-up is complete.
  
 +{{:resources:fpga:xilinx:pmod:ad5628_linux_serial.jpg?600|AD5628 Read Voltage from Serial Terminal}}
 +</wrap>
 ===== More information ===== ===== More information =====
   * [[ez>community/fpga|ask questions about the FPGA reference design]]   * [[ez>community/fpga|ask questions about the FPGA reference design]]
   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}   * Example questions: {{rss>http://ez.analog.com/community/feeds/allcontent/atom?community=2061 5 author 1d}}
resources/fpga/xilinx/pmod/ad5628.1339161388.txt.gz · Last modified: 08 Jun 2012 15:16 by Alexandru.Tofan