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resources:fpga:xilinx:kc705:adv7511 [10 Nov 2014 14:52] – [Supported Carriers] Lucian Sinresources:fpga:xilinx:kc705:adv7511 [15 Apr 2015 14:22] – Vivado Updates Dragos Bogdan
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 ==== Required Software ==== ==== Required Software ====
  
-  * Xilinx ISE 14.6 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx Vivado 2014.2
-  * A UART terminal (Tera Term/Hyperterminal) +  * A UART terminal (Tera Term/Hyperterminal) - baud rate 115200 
-      * For ISE, Baud rate 57600 for AC701/KC705/VC707 and 115200 for ZC702/ZC706/Zed. +
-      * For Vivado, Baud rate 115200 for AC701/KC705/VC707/ZC702/ZC706/Zed +
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
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 Run the **//evaluate.bat//** script. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.  Run the **//evaluate.bat//** script. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR. 
  
-**Note:** The //evaluate.bat// script assumes that the //Xilinx ISE Design Suite 14.6// is installed at this path:  //C:/Xilinx/14.6//. If the installation path on your computer is different please modify the script accordingly.+**Note:** If your Xilinx installation path is different than the one specified in the //evaluate.bat//please modify the script accordingly.
  
 If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.  If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. 
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 The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices Github.\\ The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices Github.\\
 \\ \\
-<WRAP round important 80%> 
-\\ 
-The software project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links below. 
-</WRAP> 
  
 **Evaluation Scripts:** **Evaluation Scripts:**
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   * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].   * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].
 </WRAP> </WRAP>
-===== Tar file contents ===== 
- 
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details. 
- 
-| license.txt | ADI license & copyright information. | 
-| system.mhs  | MHS file. | 
-| system.xmp  | XMP file (use this file to build the reference design). | 
-| data/       | UCF file and/or DDR MIG project files. | 
-| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). | 
-| sw/         | Software (Xilinx SDK) & bit file(s). | 
-| cf_lib/edk/pcores/     | Reference design core file(s) (Xilinx EDK). | 
- 
  
 ===== More information ===== ===== More information =====
resources/fpga/xilinx/kc705/adv7511.txt · Last modified: 08 Feb 2021 13:21 by Iulia Moldovan