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resources:fpga:xilinx:interposer:cn0202 [16 Nov 2012 17:36] – [Evaluation Boards] Lars-Peter Clausen | resources:fpga:xilinx:interposer:cn0202 [04 Dec 2013 10:05] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-CN0202 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources:fpga:xilinx:interposer: | + | \\ |
- | + | * **AD5662 Driver:** https:// | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5750 Driver:** https://github.com/ |
- | + | * **CN0202 Commands:** https:// | |
- | ^ **Folder** ^ **Description** ^ | + | |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | * **EDK KC705 Reference |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | \\ |
- | | Software | Contains the source files of the software | + | </ |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-CN0202-SDPZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | **Section B** is used to load a digital value to AD5662. | + | |
- | **Section C** is used to display | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage | ||
+ | </ | ||
- | **Section D** is used to toggle | + | |
+ | * Connect the JTAG and UART cables | ||
- | **Section E** is used to modify | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-CN0202 reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **register=** | Write a value to the DAC register. Accepted values:\\ 0 .. 65535 - value to be written in register. | | ||
+ | | **register? | ||
+ | | **ad5750clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets the CLR pin low.(default)\\ 1 - sets the CLR pin high. | | ||
+ | | **ad5750clrPin? | ||
+ | | **addressA0=** | Sets the value of A0 address bit(JP1). Accepted values:\\ 0 - address | ||
+ | | **addressA0? | ||
+ | | **range=** | Sets the output range for AD5750. Accepted values:\\ 0 -> 0V to 5V.\\ 1 -> 0V to 6V.\\ 2 -> 0V to 10V.\\ 3 -> 0V to 12V.\\ 4 -> -2.5V to +2.5V.\\ 5 -> -5V to +5V.\\ 6 -> -6V to +6V.\\ 7 -> -10V to +10V.\\ 8 -> -12V to +12V.\\ 9 -> 4mA to 20mA(internal).\\ 10 -> 4mA to 20mA(external).\\ 11 -> 0mA to 20mA(internal).\\ 12 -> 0mA to 20mA(external).\\ 13 -> 0mA to 24mA(internal).\\ 14 -> 0mA to 24mA(external).\\ 15 -> -20mA to +20mA(internal).\\ 16 -> -20mA to +20mA(external).\\ 17 -> -24mA to +24mA(internal).\\ 18 -> -24mA to +24mA(external).\\ 19 -> 3.92mA to 20.4mA(internal).\\ 20 -> 0mA to 20.4mA(internal).\\ 21 -> 0mA to 24.5mA(internal). | | ||
+ | | **range?** | Displays | ||
+ | | **fault?** | Displays the list of possible faults. | | ||
+ | |||
+ | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. | ||
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |