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resources:fpga:xilinx:interposer:cn0150 [16 Nov 2012 17:44] – [Evaluation Boards] Lars-Peter Clausenresources:fpga:xilinx:interposer:cn0150 [13 Nov 2013 14:23] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>EVAL-CN0150A-SDPZ|EVAL-CN0150A-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-CN0150A-SDPZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>EVAL-CN0150A-SDPZ|EVAL-CN0150A-SDPZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-CN0150A-SDPZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:cn0150.jpg?400 }} {{ :resources:fpga:xilinx:interposer:cn0150.jpg?400 }}
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   * [[adi>/static/imported-files/circuit_notes/CN0150.pdf|EVAL-CN0150A-SDP evaluation board user guide]]   * [[adi>/static/imported-files/circuit_notes/CN0150.pdf|EVAL-CN0150A-SDP evaluation board user guide]]
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-CN0150 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:fpga:xilinx:interposer:cn0150_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD7887 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD7887 
-The following table presents a short description the reference design archive contents. +  * **CN0150 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/CN0150 
- +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common 
-^ **Folder** ^ **Description** ^ +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</WRAP>
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-CN0150A-SDPZ** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:cn0150_interface.png?700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. +
- +
-**Section B** is used to select the sample size and to initiate a data acquisition.  The value of the "Sample Size" slider controls the number of datapoints to collect. From these datapoints is calculated an average value, which is stored in ADC Code Column (the position is auto incremented). **//Acquire Data//** button initiates a data acquisition. +
- +
-**Section C** is used to store the calibration data and to display the calculated information. The calibration is performed by applying four known signal levels to the ADL5902 and measuring the corresponding output codes from the ADC. The calibration points chosen should be within the linear operating range of the device. In this example, calibration points at -30 dBm, -20 dBm, -10 dBm, and 0 dBm were used. +
- +
-<note> +
-User has to add manually ADC Code and Input Power for each signal, in the Calibration Data section. Frequency and temperature are optional. Slope and Intercept are calculated by the interface. +
-</note> +
- +
-The SLOPE and INTERCEPT calibration coefficients are calculated using the equations: +
- +
-  * SLOPE1 = ( CODE _1 – CODE_2) / (PIN_1 - PIN_2) +
- +
-  * INTERCEPT1 = CODE_1 / (SLOPE_ADC × PIN_1) +
- +
-This calculation is then repeated using CODE_2/CODE_3 and CODE_3/CODE_4 to calculate SLOPE2/INTERCEPT2 and SLOPE3/INTERCEPT3, respectively.+
  
-When the circuit is in operation in the field, these calibration coefficients are used to calculate an unknown input power level, PIN, using the equation:+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-  * PIN = (CODE / SLOPE) + INTERCEPT+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-In order to retrieve the appropriate SLOPE and INTERCEPT calibration coefficients during circuit operation, the observed CODE from the ADC must be compared to CODE_1, CODE_2, CODE_3, and CODE_4. For example if the CODE from the ADC is between CODE_1 and CODE_2, then the SLOPE1 and INTERCEPT1 should be used.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-CN0150 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **calibration=** | Makes a two points calibration. Accepted values:\\ power input1:\\ -50 .. -5 - first point input power in [dBm].\\ power input2:\\ -50 .. -5 - second point input power in [dBm]. | 
 +| **pinCalc?** | Displays the calculated input power in [dBm]. | 
 +| **error?** | Displays the error associated with the last input power calculation. Accepted values:\\ -50 .. -5 - true input power in [dBm]. | 
  
-<note> +Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
-The interface chooses the slope and intercept for each ADC code and calculates the Power. For the error to be calculated, it is necessary to add manually the Input Power. Frequency and temperature are optional. +
-</note>+
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board's user guide. +{{page>import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:tools-software:linux-drivers:iio-adc:ad7887|AD7887 IIO ADC Linux Driver]]   * [[resources:tools-software:linux-drivers:iio-adc:ad7887|AD7887 IIO ADC Linux Driver]]
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/cn0150.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

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