This document presents the steps to setup an environment for using the EVAL-ADF4156SD1Z evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-ADF4156SD1Z Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:
The EVAL-SDP-CS1Z controller board is Serial Interfaces Only, low cost, reduced functionality controller board. It has a USB to Serial Engine at its core. It connects to the PC through a USB 2.0 high speed port. The SDP-S has a single 120 pin connector and exposes SPI, I2C and GPIO interfaces to connected SDP daughter boards.
The EVAL-ADF4156SD1Z is designed to allow the user to evaluate the performance of the ADF4156 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4156 synthesizer, an SMA connector for the reference input, power supplies, and an RF output. There is also a footprint for a loop filter and a VCO on board.
The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|Microblaze||Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
|uCProbeInterface||Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory.|
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
Set target board communication protocol as RS-232
Setup RS-232 communication settings
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-ADF4156SD1Z evaluation board.
Section A allows turning the communication with the Evaluation Board ON or OFF by toggling the switch. The green LED on the switch will turn on when communication is active. Before pressing the ON/OFF switch, make sure you select the desired Device Initialization Procedure. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.
Section B allows controlling the output on MUXOUT. Set to 1 for DVdd, 2 for GND or 7 for SDO (can be used to test if communication with board is active).
Section C allows setting Fractional, Integer, Phase, Current, R Counter and Modulus Values. See pg. 17 of datasheet for calculated examples of these values.
Section D allows setting or clearing certain control bits in Register R2 and R3. See datasheet pg. 13 for details.
Section E selects Clkock Divider Mode.
Section F selects Clock Divider Value.
Section G is used to apply settings. After setting everything as desired, press this button to send data to the ADF4156.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: