This document presents the steps to setup an environment for using the EVAL-ADF4106SD1Z evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-ADF4106SD1Z Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:
The EVAL-SDP-CS1Z controller board is Serial Interfaces Only, low cost, reduced functionality controller board. It has a USB to Serial Engine at its core. It connects to the PC through a USB 2.0 high speed port. The SDP-S has a single 120 pin connector and exposes SPI, I2C and GPIO interfaces to connected SDP daughter boards.
The EVAL-ADF4106SD1Z is designed to allow the user to evaluate the performance of the ADF4106 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4106 synthesizer, an SMA connector for the reference input, power supplies, and an RF output. There is also a footprint for a loop filter and a VCO on board.
The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|Microblaze||Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
|uCProbeInterface||Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory.|
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
Set target board communication protocol as RS-232
Setup RS-232 communication settings
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-ADF4106SD1Z evaluation board.
Section A allows for the communication with the board to be activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. Before pressing the ON/OFF switch, make sure you select the desired Device Initialization Procedure. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems.
Sections B, C and D allow for configuration of each latch on the ADF4106.
Section B allows for the configuration of the Reference Counter Latch. The LDP switch allows setting the number of consecutive cycles of phase delay that must occur before Lock Detect is Set (0 = 3 Cycles, 1 = 5 Cycles). ABP2 and ABP1 allow setting the AntiBackLash Pulse Width. The Slider allows setting the R Divider. Pressing the Write R button programs the R Counter latch.
Section C allows for the configuration of the N Counter Latch. The CP Gain switch allows toggling between different settings for the charge pump. The B Slider allows setting the B Counter value, while the A Slider allows setting the value for the A Counter. The Write N button programs the N Counter Latch.
Sections D allows programming both the Initialization Latch and the Function Latch. The CE, PD2 and PD1 switches are user to select the Power Down Mode. Current Setting 2 and Current Setting 1 sliders are used to set the value of Icp (mA). Timer Control sets the timeout in PFD CYCLES. MUXOUT slider is used to select different functions for the MUXOUT pin. Fastlock can be enabled by toggling the Fastlock EN switch, while the Counter RST switch is used to reset the counters. Pressing the Write Func button will program the Function Latch. Pressing the Write INIT button will program the Initialization Latch.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: