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This version (31 Oct 2013 10:58) was approved by CsomI.The Previously approved version (19 Nov 2012 18:55) is available.Diff

ADF4002 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Evaluation Boards

Overview

This document presents the steps to setup an environment for using the EVAL-ADF4002SD1Z evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-ADF4002SD1Z Evaluation Board with the Xilinx KC705 board.

img_adf4001.jpg

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:

The EVAL-SDP-CS1Z controller board is Serial Interfaces Only, low cost, reduced functionality controller board. It has a USB to Serial Engine at its core. It connects to the PC through a USB 2.0 high speed port. The SDP-S has a single 120 pin connector and exposes SPI, I2C and GPIO interfaces to connected SDP daughter boards.

The EVAL-ADF4002SD1Z is designed to allow the user to evaluate the performance of the ADF4002 frequency synthesizer, used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Figure 1 shows the board, which contains the ADF4002 synthesizer, an SMA connector for the reference input, power supplies, and an RF output. There is also a footprint for a loop filter and a VCO on board.

The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a standalone PFD and charge pump.

More information

Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 14.6.
  • UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200.

Downloads

Hardware setup


Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.

Reference Project Overview

The following commands were implemented in this version of EVAL-ADF4002SD1Z reference project for Xilinx KC705 FPGA board.

Command Description
help? Displays all available commands.
setregister= Update the selected latch with the current set ups. Accepted value:
latch:
0 - Reference latch
1 - N Counter Latch
2 - Function Latch
3 - Initialization Latch
value:
24 bit values, you can find more information about the registers in the data sheet
getregister? Print the specified latch values in a human readable format. Accepted value:
latch:
0 - Reference latch
1 - N Counter Latch
2 - Function Latch
3 - Initialization Latch
setfrequency= Set the VCO frequency. Accepted value:
5 .. 400 - betwwen 5Mhz and 400Mhz
getfrequency? Print the actual VCO frequency.

Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.

The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. terminal_kc705.jpg

Software Project Setup

The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design:

Github Repository

  • From this entire repository you will use cf_sdp_kc705 folder. This is common for all KC705 projects.

EDK KC705 project

  • Open the Xilinx SDK. When the SDK starts, it asks you to provide a folder where to store the workspace. Any folder can be provided. Make sure that the path where it is located does not contain any spaces.
  • In the SDK select the File→Import menu option to import the software projects into the workspace.

Import Projects

  • In the Import window select the General→Existing Projects into Workspace option.

Existing Projects Import

  • In the Import Projects window select the cf_sdp_kc705 folder as root directory and check the Copy projects into workspace option. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

Projects Import

  • The Project Explorer window now shows the projects that exist in the workspace without software files.

Project Explorer

  • Now the software must be added in your project. For downloading the software, you must use 3 links from Github given in Downloads section. From there you'll download the specific driver, the specific commands and the Xilinx Boards Common Drivers(which are commons for all Xilinx boards). All the software files downloaded must be copied in src folder from sw folder.

Project complete

  • Before compilation in the file called Communication.h you have to uncomment the name of the device that you currently use. In the picture below there is an example of this, which works only with AD5629R project. For another device, uncomment only the respective name. You can have one driver working on multiple devices, so the drivers's name and the uncommented name may not be the same for every project.

Communication.h

  • The SDK should automatically build the project and the Console window will display the result of the build. If the build is not done automatically, select the Project→Build Automatically menu option.
  • If the project was built without any errors, you can program the FPGA and run the software application.
13 Aug 2013 09:22 · Lucian Sin

More information

28 May 2012 15:18