This document presents the steps to setup an environment for using the EVAL-ADF4001SD1Z evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-ADF4001SD1Z Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices System Demonstration Platform (SDP). The SDP consists of a:
The EVAL-SDP-CS1Z controller board is Serial Interfaces Only, low cost, reduced functionality controller board. It has a USB to Serial Engine at its core. It connects to the PC through a USB 2.0 high speed port. The SDP-S has a single 120 pin connector and exposes SPI, I2C and GPIO interfaces to connected SDP daughter boards.
The EVAL-ADF4001SD1Z is designed to allow the user to evaluate the perfor-mance of the ADF4001 frequency synthesizer for phase-locked loops (PLLs). Figure 1 shows the board, which contains the ADF4001 synthesizer, an SMA connector for the reference input, power supplies, and an RF output. There is also a footprint for a loop filter and a VCO on board.
The ADF4001 frequency synthesizer can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator) or VCXO (Voltage Controlled Crystal Oscillator). The N min value of 1 allows flexibility in clock generation.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|Microblaze||Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
|uCProbeInterface||Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory.|
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
Set target board communication protocol as RS-232
Setup RS-232 communication settings
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-ADF4001SD1Z evaluation board.
Section A allows for the communication with the board to be activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. Before pressing the ON/OFF switch, make sure you select the desired Device Initialization Procedure. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board. See the Troubleshooting section for indications on how to fix the communication problems. The Error LED will indicate that the data received on the SDO pin is different than data sent. If the Function Latch or Initialization Latch is written, with a different MUXOUT value than 6, this LED will be activated. To reset the LED, the board must be deactivated and reactivated, case in which the Initialization procedure will set MUXOUT to 6.
Sections B to E allow for configuration of each latch on the ADF4001.
Section B allows for the configuration of the Reference Counter Latch. The LDP switch will toggle on or off the Lock Detect Precision bits. The TBS and ABW sliders will configure the Test Mode Bits and Anti Backlash Width bits respectively. The 14 Bit Reference Counter allows for the configuration of the counter. The last numerical display will display the resulting value in a decimal format. By toggling the Write switch in this section, a single write will be performed on the Reference Counter Latch with the programmed value.
Section C allows for the configuration of the N Counter Latch. The CPG switch toggles the CP Gain bit. The 13 Bit N Counter allows for the configuration of the N counter. The last numerical display in the row will display the resulting value in a decimal format. By toggling the Write switch, a single write will be performed on the N Counter Latch, with the value displayed.
Sections D and E have the same structure. The difference between these two latches is that when the Initialization Latch is programmed, there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at a load point when the N counter data is latched, and the device will begin counting in close phase alignment. PD2 switch toggles the Power Down 2 pin. The CS2 and CS1 sliders will configure the Current Setting 2 and Current Setting 1 bits respectively. The Timer Counter Control can be configured through the TCC slider. Next, the switches configure the Fastlock Mode, Fastlock Enable, CP Three-State and Phase Detector Polarity bits. The MUX slider allows to select what is to be available on the MUXOUT pin. By default, at initialization, this has the value 6 set, in order to be able to use this pin as SDO. PD1 switch allows for setting the Power Down 1 bits. Lastly, the CR switch allows for resetting the R and N counters.
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: