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====== AD9739A Evaluation Board, DAC-FMC Interposer & Xilinx Reference Design ======
 
<note warning>**NOTE:**\\
Support for the eval-ad9739a is discontinued  starting with 2022_R2 Kuiper Linux release and it will not be supported in future releases. Last release in which pre-build files can be found is 2021_r2. Check this [[:resources:tools-software:linux-software:adi-kuiper_images:release_notes|link]] to see all Kuiper releases.
</note>

===== Introduction =====

The [[adi>AD9739A]] is a 14-bit, 2.5GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing wideband signals from DC up to 3 GHz. This reference design includes a DDS generator that drives both ports of the device. The programming is done via the USB-SPI interface.

===== Supported Devices =====

  * [[adi>en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board]]
  * [[adi>en/evaluation/ad-dac-fmc/eb.html|DAC FMC Interposer Board]]


===== Supported Carriers =====

  * [[xilinx>ML605]] 
  * [[xilinx>KC705]] 
  * [[xilinx>VC707]] 



===== Quick Start Guide =====

The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT). The notes below refer to ML605, but the procedure is same for all the boards.

==== Required Hardware ====

  * ML605/KC705/VC707 board 
  * AD9739A-EBZ board & Power supply
  * DAC FMC interposer board
  * Signal/Clock generator (2.5GHz)
  * Spectrum Analyzer

==== Required Software ====

  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
  * ADI DPG DAC Software Suite [[/resources/eval/dpg/dacsoftwaresuite|available here]].

==== Bit file ====

  * Download the gzip file and extract the **sw/cf_ad9739a_ebz<board>.bit** file.

==== Running Demo (SDK) Program ====


To begin make the following connections (see image below):

  * Connect the AD9739A-EBZ board to the FMC Interposer board.
  * Connect the interposer board to the **FMC-LPC** connector of ML605 board.
  * Connect power to ML605 and the AD9739A-EBZ boards.
  * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on ML605.
  * Connect a USB cable to the AD9739A-EBZ board.
  * Connect an external clock source to AD9739A-EBZ board's J3 SMA connector.
  * Connect a spectrum analyzer to AD9739A-EBZ board's J1 SMA connector.

Setup the clock source to be 2.5GHz. If you wish to run the device at a different clock rate, please change the SDK c program accordingly. After the hardware setup, turn the power on to the ML605 and the AD9739A-EBZ boards.
 
{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_setup.jpg?200|Hardware setup}}

Start ADI- AD9739A SPI program (see screenshot below)-

  * (1) click on "Run Continously" button.
  * (2) click on "MU_ENA" button.
  * (3) make sure that "MU_LCK" has turned green.

{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_usb_spi.jpg?200|Hardware setup}}

Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.

{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_impact.jpg?200|IMPACT}}

If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.

{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_uart.jpg?200|Terminal}}

Now enable the receivers via the ADI- AD9739A SPI program (see screenshot above)-

  * (4) click on "RCV_ENA" button.
  * (5) click on "RCV_LOOP" button.
  * (6) make sure that "RCV_LCK" and "RCV_TRACK" has turned green.

After DDS is enabled, you should see the spectrum analyzer displaying the 300MHz tone.

{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_spectrum.gif?200|Terminal}}

===== Using the reference design =====

==== Functional description ====

The reference design consists of a DDS module and a lvds interface.

The DDS module consists of a Xilinx DDS core and DDR based DDS. Internally the DDS runs at fDAC/3 clock. The output samples are interleaved and driven by the lvds interface.

==== Registers ====

Refer to the regmap.txt file inside the pcore.
 
===== Downloads =====

FPGA Referece Designs:
<WRAP round download 80%>
  * **ML605 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_edk_14_4_2013_03_08.tar.gz}}
  * **KC705 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_kc705_edk_14_4_2013_03_08.tar.gz}}
  * **VC707 ** {{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_vc707_edk_14_4_2013_03_08.tar.gz}}
</WRAP>

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.

<WRAP round help 80%>
  * Questions? [[ez>community/fpga|Ask Help & Support]].
</WRAP>



===== Tar file contents =====

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.

| license.txt | ADI license & copyright information. |
| system.mhs  | MHS file. |
| system.xmp  | XMP file (use this file to build the reference design). |
| data/       | UCF file and/or DDR MIG project files. |
| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). |
| sw/         | Software (Xilinx SDK) & bit file(s). |
| cf_lib/edk/pcores         | The pcores directory. |


===== More information =====

  * [[http://www.vita.com/fmc|VITA's FMC info]]
  * [[ez>community/fpga|Ask questions about the FPGA reference design]]
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