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resources:fpga:xilinx:interposer:ad9671 [12 Oct 2012 16:45] – removed line breaks rejeesh kuttyresources:fpga:xilinx:interposer:ad9671 [21 Mar 2013 18:25] – [Downloads] rejeesh kutty
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 The [[adi>AD9671]] is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), a CW harmonic rejection I/Q demodulator with programmable phase rotation, an anti-aliasing filter (AAF), an analog-to-digital converter (ADC), and a digital demodulator and decimator for data processing and bandwidth reduction. This reference design includes the device data capture via the JESD204B serial interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI. The [[adi>AD9671]] is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), a CW harmonic rejection I/Q demodulator with programmable phase rotation, an anti-aliasing filter (AAF), an analog-to-digital converter (ADC), and a digital demodulator and decimator for data processing and bandwidth reduction. This reference design includes the device data capture via the JESD204B serial interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI.
  
-**HW Platform(s):** [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]], [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9671/products/EVAL-AD9671/eb.html|AD9671 Evaluation Board (ADI)]],  ADC FMC Interposer Board (ADI) \\ +===== Supported Devices ===== 
-**System:** Microblaze, AXI, UART+ 
 +  * [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9671/products/product.html#product-evaluationkits| AD9671 Evaluation Board]] 
 +  * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html| High Speed ADC FMC Interposer]] 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx> KC705]]  
 + 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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 The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9671 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9671 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
  
-The JESD core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.+The JESD core and AD9671 core has an AXI lite interface that allows control and monitoring of the capture process.
  
  
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9671_ebz.tar.gz|KC705 Reference Design Source Code}}\\+FPGA Referece Designs: 
 +<WRAP round download 80%> 
 +  * **KC705 (Source files) ** {{:resources:fpga:xilinx:interposer:cf_ad9671_ebz_edk_14_4_2013_03_21.tar.gz}} 
 +  * **KC705 (Bit files) ** {{:resources:fpga:xilinx:interposer:cf_ad9671_ebz_sw_14_4_2013_03_21.tar.gz}} 
 +</WRAP>
  
 +Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. For help and support, please use [[ez>community/fpga|Engineer Zone]].+<WRAP round help 80%> 
 +  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. 
 +</WRAP>
  
  
resources/fpga/xilinx/interposer/ad9671.txt · Last modified: 28 Jan 2021 19:13 by Robin Getz

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