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| resources:fpga:xilinx:interposer:ad9467 [22 Jun 2012 17:24] – [AD9467 FMC Interposer & Evaluation Board / Xilinx Reference Design] rejeesh kutty | resources:fpga:xilinx:interposer:ad9467 [08 Mar 2013 20:45] – [Downloads] rejeesh kutty |
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| The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC. | The [[adi>AD9467]] is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC) with a conversion rate of up to 250MSPS. This reference design includes the device data capture and SPI interface. The samples are written to the external DDR-DRAM on ML605. It allows programming the device and monitoring it's internal registers via SPI. It also allows programming the [[adi>AD9517-4]] clock chip as an alternative clock source on the board. The board also provides other options to drive the clock to the ADC. |
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| **HW Platform(s):** [[http://www.xilinx.com/products/boards-and-kits/EK-V6-ML605-G.htm|Virtex-6 ML605 (Xilinx)]], [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm|Kintex-7 KC705 (Xilinx)]] or [[http://www.xilinx.com/products/boards-and-kits/EK-V7-VC707-G.htm|Virtex-7 VC707 (Xilinx)]] [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9467/products/EVAL-AD9467/eb.html|AD9467 Evaluation Board (ADI)]], ADC FMC Interposer Board (ADI) \\ | ===== Supported Devices ===== |
| **System:** Microblaze, AXI, UART | |
| | * [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9467/products/EVAL-AD9467/eb.html|AD9467 Evaluation Board]] |
| | * [[http://www.analog.com/en/evaluation/eval-adc-fmc-int/eb.html | ADC-FMC Interposer A]] |
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| | ===== Supported Carriers ===== |
| | |
| | * [[xilinx> ML605]] |
| | * [[xilinx> KC705]] |
| | * [[xilinx> VC707]] |
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| ===== Quick Start Guide ===== | ===== Quick Start Guide ===== |
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| ==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== |
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| <note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details. | |
| </note> | |
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| To begin make the following connections (see image below): | To begin make the following connections (see image below): |
| ===== Downloads ===== | ===== Downloads ===== |
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| {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz.tar.gz|ML605 Reference Design Source Code}}\\ | FPGA Referece Designs: |
| {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_kc705.tar.gz|KC705 Reference Design Source Code}}\\ | <WRAP round download 80%> |
| {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_vc707.tar.gz|VC707 Reference Design Source Code}}\\ | * **ML605 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_edk_14_4_2013_03_08.tar.gz}} |
| | * **KC705 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_kc705_edk_14_4_2013_03_08.tar.gz}} |
| | * **VC707 ** {{:resources:fpga:xilinx:interposer:cf_ad9467_ebz_vc707_edk_14_4_2013_03_08.tar.gz}} |
| | </WRAP> |
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| | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. |
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| | <WRAP round help 80%> |
| | * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]]. |
| | </WRAP> |
| |
| ===== Tar file contents ===== | ===== Tar file contents ===== |
