Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision |
| resources:fpga:xilinx:interposer:ad9250 [18 Apr 2013 13:32] – [Running Demo (SDK) Program] Lucian Sin | resources:fpga:xilinx:interposer:ad9250 [23 Apr 2013 23:52] – add link for other board Robin Getz |
|---|
| |
| The [[adi>AD9250]] is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring its internal registers via SPI. | The [[adi>AD9250]] is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on the carrier. It allows programming the device and monitoring its internal registers via SPI. |
| | |
| | A native FMC card with the [[adi>AD9250]] can be found [[../fmc/ad-fmcjesdadc1-ebz|FMCJESDADC1 Board]] |
| |
| ===== Supported Devices ===== | ===== Supported Devices ===== |
