Table of Contents
AD971x/AD911x-DPG2 FMC Interposer & Evaluation Board / Xilinx ML-605 Reference Design
The AD9114/AD9115/AD9116/AD9117 are pin-compatible dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC® converters are optimized for the transmit signal path of commu-nication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9114/AD9115/AD9116/AD9117 offer exceptional ac and dc performance and support update rates up to 125 MSPS. The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9114/AD9115/AD9116/AD9117 make them well suited for portable and low power applications.
HW Platform(s): Virtex-6 ML605 (Xilinx), AD9114 Evaluation Board (ADI) / AD9115 Evaluation Board (ADI) / AD9116 Evaluation Board (ADI) / AD9117 Evaluation Board (ADI), DAC FMC Interposer Board (ADI)
System: Microblaze, AXI, UART
Quick Start Guide
The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT).
- ML605 board
- AD911x-DPG2-EBZ board
- DAC FMC interposer board
- Any PIC ICSP Programmer (e.g. PICkit 2 or PICkit 3 from Microchip)
- Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
- MPLAB IDE (in order to program the PIC on the AD911x-DPG2-EBZ Board)
- A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
- Download the zip file and extract the AD911x_SPI_Adapter.hex and AD911x.bit files in the project *.zip archive, located in the “sw” folder (../ad911x/sw/AD911x.bit). (where x is 4,5,6 or 7)
Running Demo (SDK) Program
If you are not familiar with ML605 and/or Xilix tools, please visit
http://www.xilinx.com/products/boards/ml605/reference_designs.htm for details.
Extract the project from the archive file (AD911x.zip) to the location you desire.
To begin make the following connections (see image below):
Programming the PIC
- Connect the USB cable from the PC to the AD911x-DPG2-EBZ board.
- Connect the programming cables from the PIC ICSP to the programming pins on connector XP1 as follows:
- PGD 1
- PGC 3
- MCLR 5
- VDD 2
- GND 6
- Program the PIC using the AD911x_SPI_Adapter.hex file found in the project *.zip archive.
- Disconnect the programming cables and the USB Cable from the AD911x-DPG2-EBZ board.
- Connect the AD911x-DPG2-EBZ board to the FMC Interposer board.
- Connect the FMC Interposer board to the FMC-LPC connector of ML605 board.
- Connect power cable to ML605.
- Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
- Turn on the ML605 Board
- Connect a USB cable to the AD911x-DPG2-EBZ board.
Programming the FPGA
Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Start a UART terminal (set to 115200 baud rate) and then program the device using the bit file provided in the project *.zip archive, located in the “sw” folder (../ad911x/sw/AD911x.bit).
Setting up uC/Probe
Launch Micrium uC/Probe and load the interface located in the project folder (../ad911x/sw/AD911x_Interface.wsp). In options, select RS-232 and set Baud Rate to 115200.
Click Play, and afterwards click on the ON/OFF Button. The Green LED on the button should light up. Set the options you desire by clicking on the red buttons and moving the sliders. After you are finished setting up the device, press “SEND AD911x SETTINGS” button. Now the device is programmed, and you should see the results on the S4 and S6 connectors on the AD911x Evaluation Board.
The User Interface is divided in 13 sections, described below:
- Section 1 Communication with the board is activated / deactivated by toggling the ON/OFF Switch
- Section 2 Modifies data format sent to the AD911x by toggling the switches ON or OFF:
- DATADIR sets the transmission mode (ON = LSB First, OFF = MSB First)
- LNGINS sets the number of address bits used by the Instruction Word (ON = 13 bits, OFF = 5 bits)
- Section 3 Modifies the way data is received from the DDS Module:
- TWOS sets the input data format (ON = Twos complement, OFF = Unsigned Binary)
- IFIRST selects pairing of input data (ON = I First on data input pads, OFF = Q First on data input pads)
- IRISING selects data latch edge (ON = I data latched on rising edge, OFF = Q data latched on rising edge)
- SIMUL selects DCLKIO type (ON = do not allow simultaneous input and output on DCLKIO, OFF = allow simultaneous input and output on DLCKIO)
- Section 4 is used to select IRset and QRset Resistor values, using the corresponding slider
- Section 5 selects differend Power Down possibilities:
- LDOOFF sets the LDO Voltage regulator ON/OFF
- LDOSTAT shows the status of LDO Voltage regulator
- PWRDN Enables or Disables Power Supply (ON = Power Down, OFF = Power On)
- ISLEEP turns I DAC output current ON/OFF
- QSLEEP turns Q DAC output current ON/OFF
- ICLKOFF turns I DAC Clock ON/OFF
- QCLKOFF turns Q DAC Clock ON/OFF
- EXTREF selects internal voltage reference (ON = Reference OFF, OFF = Reference ON)
- Section 6
- Set IRcml and QRcml Resistor values, and also I DAC and Q DAC Gain values by using the sliders provided
- Section 7 is used to set the increment value for the DDS Core using the sliders provided
- Section 8 Set different clock modes (see datasheet pg. 42 for details)
- Section 9 Turn the Auxiliary DAC ON or OFF, set their Offset and Voltage Range
- Section 10 provides calibration options for the AD911x
- CALSELI selects calibration for I Channel
- CALSELQ selects calibration for Q Channel
- DIVSEL selects clock divide ratio by 2^n (n value selected using slider)
- CALEN starts calibration process
- CALSTATI shows the status of the calibration process for I Channel (Green = Done)
- CALSTATQ shows the status of the calibration process for Q Channel (Green = Done)
- Section 11 is used to set parameters for AD9512 Clock Distribution IC (divide ratio for Data and DAC Clock)
- Section 12 User must press the button in order for the AD911x related modifications to take place
- Section 13 User must press the button in order for the AD9512 related modifications to take place
- If you drag a slider and it doesn't change the value in the numeric indicator next to it, please press Stop and then Play again. At the bottom of the screen, the bytes/sec should be increasing with 200 per second. If they increase only with 50 per second, please press Stop and Play again.
- If you receive (Pc Port Open) at the bottom of the screen, please press Stop, close your COM port, reprogram the FPGA, launch the software and try again.
- In Section 10 please select DIVSEL so that (DCLKIO / 2^n) is between 0.5 MHz and 4 MHz for optimal Calibration results
HDL / Hardware Questions
For questions regarding the interposer hardware or the HDL reference design please state them in the FPGA Reference Designs sub-community.
For questions regarding the AD9116 chip, or the AD911x eval board, please ask them in the High Speed DAC sub-community.
For questions regarding the no-OS drivers for any of the components on the AD-FMCOMMS2-EBZ please use the Microcontroller and No-OS Driver sub-community.