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AD7656-1 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design
This document presents the steps to setup an environment for using the EVAL-AD7656-1SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD7656-1SDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
- 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
- 2. The component SDP compatible product evaluation board
- 3. Corresponding PC software ( shipped with the product evaluation board)
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
The AD7656-1 is a reduced decoupling pin- and software-compatible versions of AD7656/AD7657/AD7658. The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/ 14-/12-bit, fast, low power successive approximation ADCs in a package designed on the iCMOS® process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conven-tional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. The AD7656-1/AD7657-1/AD7658-1 feature throughput rates of up to 250 kSPS.
The EVAL-AD7656-1SDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7656-1 circuits and reduce design time. When using this evaluation board with the SDP board or Xilinx KC705 board, apply +7.5V as +Vs, a voltage between -2V and -5V as -Vs and +2.5V as VDD.
- AD7656-1 Product Info - pricing, samples, datasheet
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
- FMC-SDP adapter board
- EVAL-AD7656-1SDZ evaluation board
- Xilinx ISE 13.4
- A UART terminal (ex. TeraTerm / Hyperterminal).
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|DataCapture||Contains the script used to read data from the ADC and save it into a file on the PC.|
|Hdl||Contains the HDL driver for the AD7656-1 ADC.|
|Microblaze||Contains the EDK 13.2 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
Run the Demonstration Project
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
- Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
- Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
- Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).
- Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
- Power the ADI evaluation board.
- Start a UART terminal and set the baud rate to 115200 bps.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the data_capture.bat script located in the DataCapture folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.