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AD7450A FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design
This document presents the steps to setup an environment for using the EVAL-AD7450ASDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD7450ASDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
- 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
- 2. The component SDP compatible product evaluation board
- 3. Corresponding PC software ( shipped with the product evaluation board)
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD7450ASDZ Evaluation Board.
The EVAL-AD7450ASDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7450A circuits and reduce design time.
The AD7450A is 12-bit, high speed, low power, successive-approximation (SAR) analog-to-digital converter that feature a fully differential analog input. This part operates from a single 3 V or 5 V power supply and features throughput rates up to 1 MSPS. The part contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H), which can handle input frequencies in excess of 1 MHz with the –3 dB point being 20 MHz typically. The reference voltage is applied externally to the VREF pin and can be varied from 100 mV to 3.5 V depending on the power supply and what suits the application. The value of the reference voltage determines the common mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points.
- AD7450A Product Info - pricing, samples, datasheet
- EVAL-AD7450ASDZ evaluation board user guide is included on the CD as part of the Evaluation Board Kit
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
- FMC-SDP adapter board
- EVAL-AD7450ASDZ evaluation board
- Xilinx ISE 14.3
- A UART terminal (ex. TeraTerm / Hyperterminal).
The following table presents a short description the reference design archive contents.
|Bit||Contains the KC705 configuration file that can be used to program the system for quick evaluation.|
|DataCapture||Contains the script used to read data from the ADC and save it into a file on the PC.|
|Hdl||Contains the HDL driver for the AD7450A ADC.|
|Microblaze||Contains the EDK 14.3 project for the Microblaze softcore that will be implemented in the KC705 FPGA.|
|Software||Contains the source files of the software project that will be run by the Microblaze processor.|
Run the Demonstration Project
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
- Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
- Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
- Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).
- Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
- Power the ADI evaluation board.
- Start a UART terminal and set the baud rate to 115200 bps.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the data_capture.bat script located in the DataCapture folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.
The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.