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resources:fpga:xilinx:interposer:ad7091r [08 Aug 2012 12:19] ACozma created |
resources:fpga:xilinx:interposer:ad7091r [12 Jun 2013 15:57] (current) AdrianC removed references to AD7091 |
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| {{ :resources:fpga:xilinx:interposer:ad7091r_kc705.jpg?400 }} | {{ :resources:fpga:xilinx:interposer:ad7091r_kc705.jpg?400 }} | ||
| - | For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to Analog Devices [[/resources/eval/sdp|System Demonstration Platform]] (**SDP**). The **SDP** consists of a: | + | {{page>resources:fpga:xilinx:interposer:common_sdp}} |
| - | * a controller board, like the **[[resources/eval/sdp/sdp-b|EVAL-SDP-CB1Z]] (SDP-B)** | + | |
| - | * a compatible Analog Devices SDP [[adi>sdp#exallist|product evaluation board]] | + | |
| - | * corresponding PC software | + | |
| - | The EVAL-SDP-CB1Z controller board is part of Analog Devices SDP providing USB 2.0 high-speed connectivity to a PC computer running specific component evaluation software. Each SDP evaluation daughter board includes the necessary installation files needed for this performance testing. It's expected that the analog performance on the two platforms may differ. | + | |
| Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7091RSDZ** Evaluation Board. | Below is presented a picture of **SDP-B** Controller Board with the **EVAL-AD7091RSDZ** Evaluation Board. | ||
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| The [[adi>AD7091R]] is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | The [[adi>AD7091R]] is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | ||
| - | The EVAL-AD7091RSDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7091R circuits and reduce design time. | + | The **EVAL-AD7091RSDZ** evaluation board is a member of a growing number of boards available for the **SDP**. They were designed to help customers evaluate performance or quickly prototype new **AD7091R** circuits and reduce design time. |
| ===== More information ===== | ===== More information ===== | ||
| * [[adi>AD7091R|AD7091R Product Info]] - pricing, samples, datasheet | * [[adi>AD7091R|AD7091R Product Info]] - pricing, samples, datasheet | ||
| - | * {{:resources:fpga:altera:bemicro:user_guide_eval_10lead_pulsar.pdf|EVAL-AD7091RSDZ evaluation board user guide}} | + | * [[adi>static/imported-files/user_guides/UG-409.pdf | EVAL-AD7091RSDZ evaluation board user guide]] |
| * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] | * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]] | ||
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| ===== Required Software ===== | ===== Required Software ===== | ||
| - | * Xilinx ISE 13.4 | + | * Xilinx ISE 14.4 |
| * A UART terminal (ex. TeraTerm / Hyperterminal). | * A UART terminal (ex. TeraTerm / Hyperterminal). | ||
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| | DataCapture | Contains the script used to read data from the ADC and save it into a file on the PC. | | | DataCapture | Contains the script used to read data from the ADC and save it into a file on the PC. | | ||
| | Hdl | Contains the HDL driver for the AD7091R ADC. | | | Hdl | Contains the HDL driver for the AD7091R ADC. | | ||
| - | | Microblaze | Contains the EDK 13.2 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | | Microblaze | Contains the EDK 14.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | |
| | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | | Software | Contains the source files of the software project that will be run by the Microblaze processor.| | ||
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| ===== Hardware Setup ===== | ===== Hardware Setup ===== | ||
| - | <note important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</note> | + | <WRAP important>Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.</WRAP> |
| * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. | ||
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| {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }} | {{ :resources:fpga:xilinx:interposer:teraterm_adc.png?400 }} | ||
| - | <note tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</note> | + | <WRAP tip>The first time the data capture script is run it is possible that an error will occur while the script is trying to connect to the system. Just run the script again and the error shouldn't appear anymore.</WRAP> |
| ====== More information ====== | ====== More information ====== | ||
| - | {{page>ez_common}} | + | {{page>/resources/fpga/xilinx/interposer/ez_common}} |