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resources:fpga:xilinx:interposer:ad5790 [28 Sep 2012 11:25] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5790 [30 Sep 2013 15:25] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5790 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5790 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5790 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | + | ||
- | ===== Demonstration Project User Interface | + | |
- | + | ||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5790SDZ** evaluation board. | + | |
- | + | ||
- | {{ : | + | |
- | + | ||
- | The communication with the board is activated / deactivated by toggling the **// | + | |
- | + | ||
- | The value of the AD5790 //DAC Register// is changed using the slider located under the **//DAC Register Value (20-bit)// | + | |
- | The value of the AD5790 Clearcode Register is changed using the slider located under the **// | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting | ||
+ | </ | ||
- | The sliders | + | |
+ | * Connect the JTAG and UART cables to the KC705 and power up the FPGA board. | ||
- | The DAC’s output voltage is displayed in the numeric box having the label **//Output voltage//**. This value is computed based on the Vref+ and Vref- values. | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5790 evaluation board, you need to provide external differential supply voltage to J2 connector(for more information see: [[adi>/static/imported-files/user_guides/UG-342.pdf|EVAL-AD5790SDZ evaluation board user guide]]) and a 5V reference voltage to VREF connector | ||
+ | </ | ||
- | The values of the //Control Register’s// | ||
- | The values | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Resets | ||
+ | | **coding=** | Selects the coding style. Accepted values:\\ 0 - Two's complement coding.(default)\\ 1 - Offset binary coding. | | ||
+ | | **coding?** | Display | ||
+ | | **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 1048575 - the value written to the DAC. | | ||
+ | | **register?** | Displays last written value to the DAC register. | | ||
+ | | **voltage=** | Sets the DAC output voltage. Accepted values:\\ -10 .. +10 - desired output voltage in volts. | | ||
+ | | **voltage? | ||
+ | | **output=** | Selects the DAC output state. Accepted values:\\ 0 - Normal state.\\ 1 - Clamped via 6KOhm to AGND.(default)\\ 2 - Tristate. | | ||
+ | | **output?** | Displays the DAC output state. | | ||
+ | | **rbuf=** | Sets/resets the RBUF bit from control register. Accepted values:\\ 0 - RBUF is reset.\\ | ||
+ | | **rbuf?** | Displays | ||
- | The hardware pins can be controlled by the switches under the label " | ||
+ | Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. | ||
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> |