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resources:fpga:xilinx:interposer:ad5780 [28 Sep 2012 11:24] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5780 [30 Sep 2013 15:08] – [Reference Project Overview] Lucian Sin | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi>/ | * [[adi>/ | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | ||
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5780 reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5780 Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5780 Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | {{page> | + | ===== Hardware setup ===== |
- | ===== Demonstration Project User Interface ===== | + | <WRAP round important 80%> |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. | ||
+ | </ | ||
- | The following figure presents | + | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. |
+ | | ||
- | {{ :resources: | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5780 evaluation board, you need to provide external differential supply voltage to J2 connector(for more information see: [[adi>/ | ||
+ | </ | ||
- | The communication with the board is activated / deactivated by toggling the **// | ||
- | The value of the AD5780 | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Resets | ||
+ | | **coding=** | Selects the coding style. Accepted values:\\ 0 - Two's complement coding.(default)\\ 1 - Offset binary coding. | | ||
+ | | **coding?** | Display | ||
+ | | **register=** | Writes | ||
+ | | **register? | ||
+ | | **voltage=** | Sets the DAC output voltage. Accepted values:\\ -10 .. +10 - desired output voltage in volts. | | ||
+ | | **voltage? | ||
+ | | **output=** | Selects | ||
+ | | **output?** | Displays | ||
+ | | **rbuf=** | Sets/resets the RBUF bit from control register. Accepted values:\\ 0 - RBUF is reset.\\ 1 - RBUF is set.(default) | | ||
+ | | **rbuf?** | Displays | ||
- | The value of the AD5780 Clearcode Register is changed using the slider located under the **// | ||
- | The sliders **// | + | Commands can be executed using a serial terminal connected |
- | The DAC’s output voltage is displayed | + | The following image shows a generic list of commands |
+ | {{ : | ||
- | The values of the //Control Register’s// | + | ===== Software Project Setup ===== |
- | + | {{page> | |
- | The values of the //Software Control Register’s// | + | |
- | + | ||
- | The hardware pins can be controlled by the switches under the label " | + | |
- | + | ||
- | ===== Troubleshooting | + | |
- | + | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | |
- | * Check that the evaluation board is powered as instructed in the board' | + | |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
* [[resources: | * [[resources: | ||
{{page> | {{page> | ||
- |