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resources:fpga:xilinx:interposer:ad5757 [28 Sep 2012 11:23] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costinaresources:fpga:xilinx:interposer:ad5757 [02 Oct 2013 15:55] – [Reference Project Overview] Istvan Csomortani
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5757|EVAL-AD5757SDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5757SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5757|EVAL-AD5757SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5757SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5757.jpg }} {{ :resources:fpga:xilinx:interposer:img_ad5757.jpg }}
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 {{ :resources:fpga:altera:bemicro:ad5757_sdp1z.png?400 }} {{ :resources:fpga:altera:bemicro:ad5757_sdp1z.png?400 }}
  
-The [[adi>AD5757]] is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulat-ing the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5757.+The [[adi>AD5757]] is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5757.
  
 The **EVAL-AD5757SDZ** evaluation board is designed to help customers quickly prototype new AD5757 circuits and reduce design time. To power the AD5757SDZ evaluation board supply 15V between the AVSS (0V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage. The **EVAL-AD5757SDZ** evaluation board is designed to help customers quickly prototype new AD5757 circuits and reduce design time. To power the AD5757SDZ evaluation board supply 15V between the AVSS (0V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage.
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   * [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5757SDZ evaluation board user guide]]   * [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5757SDZ evaluation board user guide]]
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Tera Term/Hyperterminal), baud rate 115200
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * **AD5757 Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5755
 +  * **AD5757 Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5755
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
 +===== Hardware setup =====
  
-  * {{:resources:fpga:xilinx:interposer:ad5757_evalboard.zip|Reference Design Files}}+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-The following table presents a short description the reference design archive contents.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-^ **Folder** ^ **Description** ^ +<WRAP round important 80%> 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +To power on the EVAL-AD5757 evaluation board, you need to provide an external +15V AVdd and -15V AVss analog supply voltage and a +5V AVcc DC-to-DC supply voltage, which will supplies all four on-board dc-to-dc blocks and may draw as much as 0.8 A peak current per channel (for more information see: [[adi>/static/imported-files/user_guides/UG-244.pdf|EVAL-AD5757SDZ evaluation board user guide]]). 
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +</WRAP>
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. |+
  
-====== Run the Demonstration Project ======+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD5757 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **register=** | Writes to the a data register. Accepted values:\\ **Register address:**\\ 0 - DAC Data Reg \\ 2 - Gain Register \\ 3 - Gain Register All DACs \\ 4 - Offset Register \\ 5 - Offset Register All DACs \\ 6 - Clear Code Register \\ 7 - Control Register \\ **Channel:**\\ 0 .. 3 - channel A .. D. \\ **Value:**\\ 0 .. 65535 - the value written to the DAC.\\ | 
 +| **control=** | Writes to the a control register. Accepted values:\\ **Register address:**\\ 0 - Slew Rate Register \\ 1 - Main Control Register \\ 2 - DAC Control Register \\ 3 - Dc-to-dc Control Register \\ 4 - Software Register \\ **Channel:**\\ 0 .. 3 - channel A .. D. \\ **Value:**\\ 0 .. 65535 - the value written to the DAC.\\ | 
 +| **register?** | Read back the value of a specified register. Accepted values:\\ Register address : 0x00 .. 0x1A. | 
 +| **power=** | Set the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. Accepted values:\\ **Channel:**\\ 0 .. 3 - channel A .. D.\\ **Value:**\\ 0 - turn off; 1 - turn on. | 
 +| **power?** | Displays the power state of the dc-to-dc converters,DAC and internal amplifiers for the selected channel. Accepted values:\\ **Channel:**\\ 0 .. 3 - channel A .. D. | 
 +| **range=** | Set the range of the selected channel. Accepted values:\\ **Channel:**\\ 0 .. 3 - channel A .. D.\\ **Range:**\\  0 - 0 V to 5 V voltage\\ 1 - 0 V to 10 V voltage\\ 2 - -5 V to +5 V voltage\\ 3 - -10 V to +10 V voltage\\ 4 - 4 mA to 20 mA current\\ 5 - 0 mA to 20 mA current\\ 6 - 0 mA to 24 mA current| 
 +| **range?** | Displays the range of the selected channel. Accepted values: \\ **Channel:**\\ 0 .. 3 - channel A .. D.| 
 +| **voltage=** | Sets the output voltage for a selected channel. Accepted values: \\ **Channel:**\\ 0 .. 3 - channel A .. D.\\ Desired voltage(unit in V) multiplied by 1000 | 
 +| **voltage?** | Displays the output voltage for a selected channel. Accepted values:\\ **Channel:**\\ 0 .. 3 - channel A .. D.| 
 +| **current=** | Displays the output current for a selected channel. Accepted values: \\ **Channel:**\\ 0 .. 3 - channel A .. D.\\ Desired current (unit in mA) multiplied by 1000 | 
 +| **current?** | Displays the output current for a selected channel. Accepted values: \\ **Channel:**\\ 0 .. 3 - channel A .. D. | 
 +| **getStatus!** | Read back the Status register and print any faults or errors. | 
 +| **testSPI!** | Ensure that the SPI interface are working correctly. | 
 +  
 +Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-{{page>ucprobe_common}}+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-===== Demonstration Project User Interface ===== +===== Software Project Setup ===== 
- +{{page>import_workspace}}
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5757SDZ** evaluation board. +
- +
-{{ :resources:fpga:altera:bemicro:ad5757_interface.png?700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. +
- +
-**Section B** is used to select the DAC channel. +
- +
-**Section C** is used to write data into the register selected by the Selection Slider. +
- +
-Options: +
- +
-  * Write to DAC data register (individual channel write). +
-  * Write to gain register (individual channel write). +
-  * Write to gain register (all DACs). +
-  * Write to offset register (individual channel write). +
-  * Write to offset register (all DACs) . +
-  * Write to clear code register (individual channel write). +
- +
- +
-**Section D** is used to read data from the register selected by the Selection Slider. +
- +
-Options: +
- +
-  * Read from DAC data register (individual channel read). +
-  * Read from DAC control register (individual channel read). +
-  * Read from Gain register (individual channel read). +
-  * Read from Offset register (individual channel read). +
-  * Read from Clear Code register (individual channel read). +
-  * Read from Slew Rate control register (individual channel read). +
-  * Read from Status register. +
-  * Read from Main control register. +
-  * Read from DC-to-DC control register. +
- +
-**Section E** is used to write data into the DAC n Control Register. +
- +
-Options: +
- +
-  * Internal – Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. +
-  * Clear – Clear enable bit. +
-  * Output – Enables/disables the selected output channel. +
-  * Rset – Selects an internal or external current sense resistor for the selected DAC channel. +
-  * DC-DC – Powers the dc-to-dc converter on the selected channel. +
-  * Output Range – Selects the output range to be enabled. +
- +
-**Section F** is used to write data into the DC-DC Control Register. +
- +
-Options: +
- +
-  * DC-DC Comp – Selects between an internal and external compensation resistor for the dc-to-dc converter. +
-  * Phase – User programmable dc-to-dc converter phase (between channels). +
-  * Frequency – DC-to-dc switching frequency. +
-  * Max Voltage – Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. +
- +
-**Section G** is used to write data into the Main Control Register. +
- +
-Options: +
- +
-  * StartRead – Enable status readback during a write. +
-  * EWD – Enable watchdog timer. +
-  * WD Period – Select the timeout period for the watchdog timer. +
-  * OutEn All – Enables the output on all four DACs simultaneously. +
-  * DC-DC All – Powers up the dc-to-dc converter on all four channels simultaneously. +
- +
-**Section H** is used to write data into the Slew Rate Control Register. +
- +
-Options: +
- +
-  * SE – Enable SE. +
-  * SR Clock – Slew Rate Update Clock Options. +
-  * SR Step – Slew Rate Step Size Options. +
- +
-**Section I** is used to write data into the Software Register. +
- +
-Options: +
- +
-  * User Bit – This bit is mapped to Bit D11 of the status register. +
-  * Software Reset – Performs a reset of the AD5757. +
- +
-===== Troubleshooting ===== +
- +
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +
-  * Check that the evaluation board is powered as instructed in the board's user guide. +
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:tools-software:linux-drivers:iio-dac:ad5755|AD5757 IIO DAC Linux Driver]]   * [[resources:tools-software:linux-drivers:iio-dac:ad5755|AD5757 IIO DAC Linux Driver]]
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/ad5757.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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