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This version (02 Oct 2013 15:56) was approved by CsomI.The Previously approved version (28 Sep 2012 11:23) is available.Diff

AD5757 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design

Supported Devices

Evaluation Boards

Overview

This document presents the steps to setup an environment for using the EVAL-AD5757SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5757SDZ Evaluation Board with the Xilinx KC705 board.

img_ad5757.jpg

For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:

  • 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
  • 2. The component SDP compatible product evaluation board
  • 3. Corresponding PC software ( shipped with the product evaluation board)

The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.

Note: it is expected that the analog performance on the two platforms may differ.

28 Sep 2012 10:32 · Adrian Costina

Below is presented a picture of SDP-B Controller Board with the EVAL-AD5757SDZ Evaluation Board.

The AD5757 is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5757.

The EVAL-AD5757SDZ evaluation board is designed to help customers quickly prototype new AD5757 circuits and reduce design time. To power the AD5757SDZ evaluation board supply 15V between the AVSS (0V) and AVDD (+15V) inputs for the analog supply and 5V between PGND(0V) and AVCC(+5V) as DC-to-DC supply voltage.

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Getting Started

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

Required Hardware

Required Software

  • Xilinx ISE 14.6 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
  • UART Terminal (Tera Term/Hyperterminal), baud rate 115200

Downloads

Hardware setup


Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.

  • Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
  • Connect the JTAG and UART cables to the KC705 and power up the FPGA board.


To power on the EVAL-AD5757 evaluation board, you need to provide an external +15V AVdd and -15V AVss analog supply voltage and a +5V AVcc DC-to-DC supply voltage, which will supplies all four on-board dc-to-dc blocks and may draw as much as 0.8 A peak current per channel (for more information see: EVAL-AD5757SDZ evaluation board user guide).

Reference Project Overview

The following commands were implemented in this version of EVAL-AD5757 reference project for Xilinx KC705 FPGA board.

Command Description
help? Displays all available commands.
register= Writes to the a data register. Accepted values:
Register address:
0 - DAC Data Reg
2 - Gain Register
3 - Gain Register All DACs
4 - Offset Register
5 - Offset Register All DACs
6 - Clear Code Register
7 - Control Register
Channel:
0 .. 3 - channel A .. D.
Value:
0 .. 65535 - the value written to the DAC.
control= Writes to the a control register. Accepted values:
Register address:
0 - Slew Rate Register
1 - Main Control Register
2 - DAC Control Register
3 - Dc-to-dc Control Register
4 - Software Register
Channel:
0 .. 3 - channel A .. D.
Value:
0 .. 65535 - the value written to the DAC.
register? Read back the value of a specified register. Accepted values:
Register address : 0x00 .. 0x1A.
power= Set the power state of the dc-to-dc converters, DAC and internal amplifiers for the selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
Value:
0 - turn off; 1 - turn on.
power? Displays the power state of the dc-to-dc converters,DAC and internal amplifiers for the selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
range= Set the range of the selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
Range:
0 - 0 V to 5 V voltage
1 - 0 V to 10 V voltage
2 - -5 V to +5 V voltage
3 - -10 V to +10 V voltage
4 - 4 mA to 20 mA current
5 - 0 mA to 20 mA current
6 - 0 mA to 24 mA current
range? Displays the range of the selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
voltage= Sets the output voltage for a selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
Desired voltage(unit in V) multiplied by 1000
voltage? Displays the output voltage for a selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
current= Displays the output current for a selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
Desired current (unit in mA) multiplied by 1000
current? Displays the output current for a selected channel. Accepted values:
Channel:
0 .. 3 - channel A .. D.
getStatus! Read back the Status register and print any faults or errors.
testSPI! Ensure that the SPI interface are working correctly.

Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.

The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. terminal_kc705.jpg

Software Project Setup

The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design:

Github Repository

  • From this entire repository you will use cf_sdp_kc705 folder. This is common for all KC705 projects.

EDK KC705 project

  • Open the Xilinx SDK. When the SDK starts, it asks you to provide a folder where to store the workspace. Any folder can be provided. Make sure that the path where it is located does not contain any spaces.
  • In the SDK select the File→Import menu option to import the software projects into the workspace.

Import Projects

  • In the Import window select the General→Existing Projects into Workspace option.

Existing Projects Import

  • In the Import Projects window select the cf_sdp_kc705 folder as root directory and check the Copy projects into workspace option. After the root directory is chosen the projects that reside in that directory will appear in the Projects list. Press Finish to finalize the import process.

Projects Import

  • The Project Explorer window now shows the projects that exist in the workspace without software files.

Project Explorer

  • Now the software must be added in your project. For downloading the software, you must use 3 links from Github given in Downloads section. From there you'll download the specific driver, the specific commands and the Xilinx Boards Common Drivers(which are commons for all Xilinx boards). All the software files downloaded must be copied in src folder from sw folder.

Project complete

  • Before compilation in the file called Communication.h you have to uncomment the name of the device that you currently use. In the picture below there is an example of this, which works only with AD5629R project. For another device, uncomment only the respective name. You can have one driver working on multiple devices, so the drivers's name and the uncommented name may not be the same for every project.

Communication.h

  • The SDK should automatically build the project and the Console window will display the result of the build. If the build is not done automatically, select the Project→Build Automatically menu option.
  • If the project was built without any errors, you can program the FPGA and run the software application.
13 Aug 2013 09:22 · Lucian Sin

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