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resources:fpga:xilinx:interposer:ad5686r [28 Sep 2012 11:21] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costinaresources:fpga:xilinx:interposer:ad5686r [01 Oct 2013 10:47] – changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact Lucian Sin
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>AD5686R|EVAL-AD5686RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the [[http://micrium.com/page/products/tools/probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD5686RSDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>AD5686R|EVAL-AD5686RSDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit. Below is presented a picture of the EVAL-AD5686RSDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :resources:fpga:xilinx:interposer:img_ad5686r.jpg?400 }} {{ :resources:fpga:xilinx:interposer:img_ad5686r.jpg?400 }}
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 ===== More information ===== ===== More information =====
   * [[adi>AD5686R|AD5686 Product Info]] - pricing, samples, datasheet   * [[adi>AD5686R|AD5686 Product Info]] - pricing, samples, datasheet
-  * EVAL-AD5686RSDZ evaluation board user guide included on EVAL BOARD CD+  * [[adi>/static//imported-files/user_guides/UG-459.pdf | EVAL-AD5686RSDZ evaluation board user guide]]
   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://www.xilinx.com/products/boards-and-kits/EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://micrium.com/page/products/tools/probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). +  * Xilinx ISE 14.6. 
-  * [[http://micrium.com/page/products/tools/probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal), baud rate 115200. 
 +  * The EVAL-AD5686R reference project for Xilinx KC705 FPGA.
  
 ===== Downloads ===== ===== Downloads =====
 +<WRAP round download 80%>
 +\\
 +  * **AD5686R Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5686
 +  * **AD5686R Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5686
 +  * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
 +  * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
 +\\
 +</WRAP>
 +====== Run the Demonstration Project ======
  
-  * {{:resources:fpga:xilinx:interposer:ad5686r_evalboard.zip|Reference Design Files}}+===== Hardware setup =====
  
-The following table presents a short description the reference design archive contents.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</WRAP>
  
-^ **Folder** ^ **Description** ^ +  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +
-| Software | Contains the source files of the software project that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
- +
-====== Run the Demonstration Project ======+
  
-{{page>ucprobe_common}}+<WRAP round important 80%> 
 +\\ 
 +To power on the EVAL-AD5686R evaluation board, you need to apply +6V supply voltage to J3 connector of the board. 
 +</WRAP>
  
-===== Demonstration Project User Interface =====+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD5686R reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **reset!** | Activate a power-on reset. | 
 +| **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **update=** | Update the selected DAC channel with the input register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels. | 
 +| **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 65535 - value to be written in register. | 
 +| **readback=** | Read back the selected DAC channels value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D. | 
 +| **pwrMode=** | Set up the Power Mode of a selected channel. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | 
 +| **pwrMode?** | Displays the power mode for one selected DAC. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D. | 
 +| **ldacMask=** | Set up the LDAC mask register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ set/reset mask:\\ 0 - reset LDAC mask for the selected channel.\\ 1 - set LDAC mask for the selected channel. | 
 +| **ldacMask?** | Displays the LDAC register. | 
 +| **intRef=** | Turns on or off the internal reference. Accepted values:\\ 0 - turns off the internal reference.(default)\\ 1 - turns on the internal reference. | 
 +| **intRef?** | Displays the status of the internal reference. | 
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | 
 +| **ldacPin?** | Displays the value of LDAC pin. |
  
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5686r** evaluation board. 
  
-{{ :resources:fpga:altera:bemicro:ad5686r_interface.png?700 }}+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-The communication with the board is activated / deactivated by toggling the **//ON/OFF//** switch. The **//Activity//** LED turns green when the communication is active. If the **//ON/OFF//** switch is set to **//ON//** and the **//Activity//** LED is **//BLACK//** it means that there is a communication problem with the board. The sliders are used to set the value desired to be written to the AD5686R DAC Registers. The red switch is used to perform a Software Reset of the AD5686R.+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :resources:fpga:xilinx:interposer:Terminal_KC705.jpg? }}
  
-===== Troubleshooting =====+===== Software Project Setup ===== 
 +{{page>import_workspace}}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: 
-  * Check that the evaluation board is powered as instructed in the board's user guide. 
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//**. 
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. 
  
 ====== More information ====== ====== More information ======
 {{page>ez_common}} {{page>ez_common}}
resources/fpga/xilinx/interposer/ad5686r.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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